Presentation | 2016-11-30 Fast Test Pattern Reordering Based on Weighted Fault Coverage Shingo Inuyama, Kazuhiko Iwasaki, Masayuki Arai, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap between the defect level estimation at the design stage and the reported one for fabricated devices. Authors have proposed a technique that can lower the defect level for shipped VLSI chips. In this study, considering bridge and open faults, we propose fast test pattern reordering techniques. Based on distribution of critical area, we make two fault groups. Test generation is performed targeting each fault group, then the reordering is only applied to the second test pattern set. We also show the window-based reordering. Compared to the previous reordering, the proposed scheme significantly reduce processing time while test pattern count slightly increases. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | critical area / weighted fault coverage / bridge fault / open fault / test generation |
Paper # | VLD2016-61,DC2016-55 |
Date of Issue | 2016-11-21 (VLD, DC) |
Conference Information | |
Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE |
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Conference Date | 2016/11/28(3days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT) |
Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK) |
Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.) |
Assistant | Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Fast Test Pattern Reordering Based on Weighted Fault Coverage |
Sub Title (in English) | |
Keyword(1) | critical area |
Keyword(2) | weighted fault coverage |
Keyword(3) | bridge fault |
Keyword(4) | open fault |
Keyword(5) | test generation |
1st Author's Name | Shingo Inuyama |
1st Author's Affiliation | Tokyo Metropolitan University(Tokyo Metropolitan Univ.) |
2nd Author's Name | Kazuhiko Iwasaki |
2nd Author's Affiliation | Tokyo Metropolitan University(Tokyo Metropolitan Univ.) |
3rd Author's Name | Masayuki Arai |
3rd Author's Affiliation | Nihon University(Nihon Univ.) |
Date | 2016-11-30 |
Paper # | VLD2016-61,DC2016-55 |
Volume (vol) | vol.116 |
Number (no) | VLD-330,DC-331 |
Page | pp.pp.99-104(VLD), pp.99-104(DC), |
#Pages | 6 |
Date of Issue | 2016-11-21 (VLD, DC) |