| Presentation | 2016-11-28 Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta, Pieter Weckx, Ben Kaczer, Takashi Matsumoto, Hidetoshi Onodera, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a circuit analysis method using the bimodal RTN (random telegraph noise) model of the defect-centric distribution. The conventional unimodal model fails to replicate the effect of RTN on 40 nm SiON process circuits. The bimodal model takes into account defect characteristics of both HK and interface layer in gate dielectric. The proposed method estimates defect characteristics and reproduces frequency distributions by RTN. We confirm the bimodal model fully replicates the effect of RTN by comparing simulation and measurement results of 40 nm test chips. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | RTN (Random Telegraph Noise) / defect-centric distribution / variation / reliability / circuit design |
| Paper # | VLD2016-52,DC2016-46 |
| Date of Issue | 2016-11-21 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE |
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| Conference Date | 2016/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
| Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process |
| Sub Title (in English) | |
| Keyword(1) | RTN (Random Telegraph Noise) |
| Keyword(2) | defect-centric distribution |
| Keyword(3) | variation |
| Keyword(4) | reliability |
| Keyword(5) | circuit design |
| 1st Author's Name | Michitarou Yabuuchi |
| 1st Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 2nd Author's Name | Azusa Oshima |
| 2nd Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 3rd Author's Name | Takuya Komawaki |
| 3rd Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 4th Author's Name | Kazutoshi Kobayashi |
| 4th Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 5th Author's Name | Ryo Kishida |
| 5th Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 6th Author's Name | Jun Furuta |
| 6th Author's Affiliation | Kyoto Institute of Technology(KIT) |
| 7th Author's Name | Pieter Weckx |
| 7th Author's Affiliation | KU Leuven/Interuniversity Microelectronics Centre(KUL/IMEC) |
| 8th Author's Name | Ben Kaczer |
| 8th Author's Affiliation | Interuniversity Microelectronics Centre(IMEC) |
| 9th Author's Name | Takashi Matsumoto |
| 9th Author's Affiliation | University of Tokyo(Univ. of Tokyo) |
| 10th Author's Name | Hidetoshi Onodera |
| 10th Author's Affiliation | Kyoto University(Kyoto Univ.) |
| Date | 2016-11-28 |
| Paper # | VLD2016-52,DC2016-46 |
| Volume (vol) | vol.116 |
| Number (no) | VLD-330,DC-331 |
| Page | pp.pp.49-54(VLD), pp.49-54(DC), |
| #Pages | 6 |
| Date of Issue | 2016-11-21 (VLD, DC) |