| Presentation | 2016-11-29 Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB) Yusuke Yoshida, Kimiyoshi Usami, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We focus on the Standard Cell Memory (SCM) as another option to supersede SRAM for low-voltage operation. This paper describes a design of low-power SCM using Silicon-on-Thin-BOX (SOTB). In particular, we present automatic place and routing(P&R) methodology for optimal body-bias separation(BBS) for SCM. Simulation results demonstrated that proposed automatic P&R methodology can reduce wire length by 22% and energy consumption by 57% as compared to the standard digital flow. We also found that the proposed SCM operates at the minimum energy point (0.3V) with 3.7fJ energy per bit-access because we can reduce leakage energy in Near-Vth/Sub-Vth region by optimal BBS. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Silicon-on-Thin-BOX MOSFET / Body Bias / Standard Cell Memory / Ultra-low voltage operation / Low-power |
| Paper # | VLD2016-53,DC2016-47 |
| Date of Issue | 2016-11-21 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / CPSY / RECONF / CPM / ICD / IE |
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| Conference Date | 2016/11/28(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ritsumeikan University, Osaka Ibaraki Campus |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2016 -New Field of VLSI Design- |
| Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Satoru Noge(Numazu National College of Tech.) / Minoru Fujishima(Hiroshima Univ.) / Seishi Takamura(NTT) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Fumihiko Hirose(Yamagata Univ.) / Hideto Hidaka(Renesas) / Takayuki Hamamoto(Tokyo Univ. of Science) / Atsuro Ichigaya(NHK) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Satoshi Fukumoto(Hiroshima City Univ.) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Tokyo Inst. of Tech.) / Masato Motomura(Fujitsu Labs.) / Yuichiro Shibata(NII) / Fumihiko Hirose(Univ. of Tsukuba) / Hideto Hidaka(Hiroshima City Univ.) / Takayuki Hamamoto(NTT) / Atsuro Ichigaya(Nihon Univ.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) / / Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) / Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) / Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Kei Kawamura(KDDI R&D Labs.) / Keita Takahashi(Nagoya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Component Parts and Materials / Technical Committee on Integrated Circuits and Devices / Technical Committee on Image Engineering |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB) |
| Sub Title (in English) | |
| Keyword(1) | Silicon-on-Thin-BOX MOSFET |
| Keyword(2) | Body Bias |
| Keyword(3) | Standard Cell Memory |
| Keyword(4) | Ultra-low voltage operation |
| Keyword(5) | Low-power |
| 1st Author's Name | Yusuke Yoshida |
| 1st Author's Affiliation | Shibaura Institute of Technolog(Shibaura Institute of Tech.) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technolog(Shibaura Institute of Tech.) |
| Date | 2016-11-29 |
| Paper # | VLD2016-53,DC2016-47 |
| Volume (vol) | vol.116 |
| Number (no) | VLD-330,DC-331 |
| Page | pp.pp.55-60(VLD), pp.55-60(DC), |
| #Pages | 6 |
| Date of Issue | 2016-11-21 (VLD, DC) |