| Presentation | 2016-09-06 An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation Daichi Murata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents an efficient and small-scaled RNN (Recurrent Neural Network) hardware architecture based on approximation of RNN algorithm for hardware implementation. In an LSTM (Long Short-Term Memory) layer, using an approximate function instead of sigmoid function and hyperbolic function is the key to save hardware resources while keeping the accuracy of RNN results. Moreover, we propose a technique to reduce latency by simplifying pooling layer. Experimental results have shown that our LSTM architecture using the approximate function reduces computing element area by 88.6%, and memory element area by 79.1% while keeping the accuracy of RNN results. Moreover, the proposed pooling hardware architecture reduces latency by 84.3%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / RNN / LSTM / Function Approximation |
| Paper # | RECONF2016-38 |
| Date of Issue | 2016-08-29 (RECONF) |
| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2016/9/5(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Univ. of Toyama |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable Systems, etc. |
| Chair | Minoru Watanabe(Shizuoka Univ.) |
| Vice Chair | Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) |
| Secretary | Masato Motomura(Univ. of Tsukuba) / Yuichiro Shibata(Hiroshima City Univ.) |
| Assistant | Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC) |
| Paper Information | |
| Registration To | Technical Committee on Reconfigurable Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | RNN |
| Keyword(3) | LSTM |
| Keyword(4) | Function Approximation |
| 1st Author's Name | Daichi Murata |
| 1st Author's Affiliation | Kobe University(Kobe Univ.) |
| 2nd Author's Name | Tetsuya Hirose |
| 2nd Author's Affiliation | Kobe University(Kobe Univ.) |
| 3rd Author's Name | Nobutaka Kuroki |
| 3rd Author's Affiliation | Kobe University(Kobe Univ.) |
| 4th Author's Name | Masahiro Numa |
| 4th Author's Affiliation | Kobe University(Kobe Univ.) |
| Date | 2016-09-06 |
| Paper # | RECONF2016-38 |
| Volume (vol) | vol.116 |
| Number (no) | RECONF-210 |
| Page | pp.pp.69-74(RECONF), |
| #Pages | 6 |
| Date of Issue | 2016-08-29 (RECONF) |