Presentation 2016-09-05
Proposal of vertical stacked reconfigurable Fe-FET NAND logic and its application to combination logic, flip-flop and LUT
Shigeyoshi Watanabe, Tomohiro Yokota, Shoto Tamai, Takumi Sato,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # RECONF2016-29
Date of Issue 2016-08-29 (RECONF)

Conference Information
Committee RECONF
Conference Date 2016/9/5(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Univ. of Toyama
Topics (in Japanese) (See Japanese page)
Topics (in English) Reconfigurable Systems, etc.
Chair Minoru Watanabe(Shizuoka Univ.)
Vice Chair Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.)
Secretary Masato Motomura(Univ. of Tsukuba) / Yuichiro Shibata(Hiroshima City Univ.)
Assistant Takefumi Miyoshi(e-trees.Japan) / Yuuki Kobayashi(NEC)

Paper Information
Registration To Technical Committee on Reconfigurable Systems
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Proposal of vertical stacked reconfigurable Fe-FET NAND logic and its application to combination logic, flip-flop and LUT
Sub Title (in English)
Keyword(1)
1st Author's Name Shigeyoshi Watanabe
1st Author's Affiliation Shonan Institute of Technology(Shonan Inst. of Tech.)
2nd Author's Name Tomohiro Yokota
2nd Author's Affiliation DNP Data Techno Co., Ltd(DNP Data Techno)
3rd Author's Name Shoto Tamai
3rd Author's Affiliation Oi Electric Co., Ltd(Oi Electric)
4th Author's Name Takumi Sato
4th Author's Affiliation Shonan Institute of Technology(Shonan Inst. of Tech.)
Date 2016-09-05
Paper # RECONF2016-29
Volume (vol) vol.116
Number (no) RECONF-210
Page pp.pp.23-28(RECONF),
#Pages 6
Date of Issue 2016-08-29 (RECONF)