| Presentation | 2016-08-03 Performance Enhancement of Tunnel FET by Negative Capacitance Masaharu Kobayashi, Kyungmin Jang, Nozomu Ueyama, Toshiro Hiramoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | IoT devices in a sensor network require a new energy-efficient transistor which operates at ultralow voltage and power employing energy-harvesting techniques. In this paper, we propose a new steep slope transistor by combining the feature of tunnel FET(TFET) and negative capacitance FET(NCFET) which have been independently studied so far. In NCTFET, band-to-band tunneling in TFET can be enhanced by negative capacitance effect of ferroelectric gate insulator. This results in improvement of subthreshold slope. The energy efficiency of NCTFET is about 10 times higher than conventional MOSFET and TFET. Therefore, NCTFET is expected to become a new CMOS platform for IoT application. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Tunnel FET / Negative Capacitance FET / steep slope transistor / ferroelectric |
| Paper # | SDM2016-68,ICD2016-36 |
| Date of Issue | 2016-07-25 (SDM, ICD) |
| Conference Information | |
| Committee | ICD / SDM / ITE-IST |
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| Conference Date | 2016/8/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Central Electric Club |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low voltage/low power techniques, novel devices, circuits, and applications |
| Chair | Minoru Fujishima(Hiroshima Univ.) / Tatsuya Kunikiyo(Renesas) / Shigetoshi Sugawa(Tohoku Univ.) |
| Vice Chair | Hideto Hidaka(Renesas) / Takahiro Shinada(Tohoku Univ.) / Takayuki Hamamoto(東京理科大) / Hiroshi Ohtake(NHK) |
| Secretary | Hideto Hidaka(Hiroshima Univ.) / Takahiro Shinada(Univ. of Tokyo) / Takayuki Hamamoto(Tohoku Univ.) / Hiroshi Ohtake(Renesas) |
| Assistant | Takashi Hashimoto(Panasonic) / Masanori Natsui(Tohoku Univ.) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Hiroya Ikeda(Shizuoka Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Silicon Device and Materials / Technical Group on Information Sensing Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Enhancement of Tunnel FET by Negative Capacitance |
| Sub Title (in English) | |
| Keyword(1) | Tunnel FET |
| Keyword(2) | Negative Capacitance FET |
| Keyword(3) | steep slope transistor |
| Keyword(4) | ferroelectric |
| 1st Author's Name | Masaharu Kobayashi |
| 1st Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 2nd Author's Name | Kyungmin Jang |
| 2nd Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 3rd Author's Name | Nozomu Ueyama |
| 3rd Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 4th Author's Name | Toshiro Hiramoto |
| 4th Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| Date | 2016-08-03 |
| Paper # | SDM2016-68,ICD2016-36 |
| Volume (vol) | vol.116 |
| Number (no) | SDM-172,ICD-173 |
| Page | pp.pp.127-130(SDM), pp.127-130(ICD), |
| #Pages | 4 |
| Date of Issue | 2016-07-25 (SDM, ICD) |