Presentation 2016-08-10
A Study of Execution Throttling for Power-Constrained FPGA Accelerators
Keisuke Fujimoto, Shinya Takamaeda, Yasuhiko Nakashima,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # CPSY2016-35
Date of Issue 2016-08-01 (CPSY)

Conference Information
Committee CPSY / DC / IPSJ-ARC
Conference Date 2016/8/8(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Kissei-Bunka-Hall (Matsumoto)
Topics (in Japanese) (See Japanese page)
Topics (in English) Parallel, Distributed and Cooperative Processing
Chair Yasuhiko Nakashima(NAIST) / Michiko Inoue(NAIST)
Vice Chair Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Satoshi Fukumoto(Tokyo Metropolitan Univ.)
Secretary Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Satoshi Fukumoto(Kyoto Sangyo Univ.) / (Tokyo Inst. of Tech.)
Assistant Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST)

Paper Information
Registration To Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture
Language JPN-ONLY
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Study of Execution Throttling for Power-Constrained FPGA Accelerators
Sub Title (in English)
Keyword(1)
Keyword(2)
Keyword(3)
1st Author's Name Keisuke Fujimoto
1st Author's Affiliation Nara Institute of Science and Technology(NAIST)
2nd Author's Name Shinya Takamaeda
2nd Author's Affiliation Nara Institute of Science and Technology(NAIST)
3rd Author's Name Yasuhiko Nakashima
3rd Author's Affiliation Nara Institute of Science and Technology(NAIST)
Date 2016-08-10
Paper # CPSY2016-35
Volume (vol) vol.116
Number (no) CPSY-177
Page pp.pp.257-262(CPSY),
#Pages 6
Date of Issue 2016-08-01 (CPSY)