| Presentation | 2016-08-09 High Performance of Cache by Dynamic Control to Area Division Maika Tone, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Today, multi-core processor is widely used to improve performance of a processor. However, memory access frequency of multi-core processor is larger than that of single-core processor. Therefore, a cache system for multi-core processor may degrade system performance. There are many studies to improve cache, and cache partitioning is one of the representatives. It allocates ways to cores efficiently, but cannot allocate optimally for shared data. This paper proposes a new method, cell-allocation cache. Compared with a normal cache, on some benchmark programs, the proposed method reduces 0.92% and 0.43% of execution time and cache miss rate, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Cache / High Performance / Multi-core / Area Division |
| Paper # | CPSY2016-19 |
| Date of Issue | 2016-08-01 (CPSY) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-ARC |
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| Conference Date | 2016/8/8(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kissei-Bunka-Hall (Matsumoto) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Parallel, Distributed and Cooperative Processing |
| Chair | Yasuhiko Nakashima(NAIST) / Michiko Inoue(NAIST) |
| Vice Chair | Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Satoshi Fukumoto(Tokyo Metropolitan Univ.) |
| Secretary | Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Satoshi Fukumoto(Kyoto Sangyo Univ.) / (Tokyo Inst. of Tech.) |
| Assistant | Takeshi Ohkawa(Utsunomiya Univ.) / Shinya Takameda(NAIST) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | High Performance of Cache by Dynamic Control to Area Division |
| Sub Title (in English) | |
| Keyword(1) | Cache |
| Keyword(2) | High Performance |
| Keyword(3) | Multi-core |
| Keyword(4) | Area Division |
| 1st Author's Name | Maika Tone |
| 1st Author's Affiliation | Mie University(Mie Univ.) |
| 2nd Author's Name | Takahiro Sasaki |
| 2nd Author's Affiliation | Mie University(Mie Univ.) |
| 3rd Author's Name | Yuki Fukazawa |
| 3rd Author's Affiliation | Mie University(Mie Univ.) |
| 4th Author's Name | Toshio Kondo |
| 4th Author's Affiliation | Mie University(Mie Univ.) |
| Date | 2016-08-09 |
| Paper # | CPSY2016-19 |
| Volume (vol) | vol.116 |
| Number (no) | CPSY-177 |
| Page | pp.pp.119-124(CPSY), |
| #Pages | 6 |
| Date of Issue | 2016-08-01 (CPSY) |