| 講演名 | 2016-06-02 [Invited Talk] Modeling and Measuring Vertical Interconnects with Impedance Control Over a Wide Frequency Range Kuan-Chung Lu(National Sun Yat-sen Univ.), Tzyy-Sheng Horng(National Sun Yat-sen Univ.), |
|---|---|
| PDFダウンロードページ |  PDFダウンロードページへ |
| 抄録(和) | The advantages of vertical interconnects include superior electrical transmissions for stacked dies, higher I/O density, and heterogeneous integration. Despite the shorter physical length and superior electrical properties of the vertical interconnects, the arrangement of corresponding grounding pins drastically affects the characteristic impedance, resulting in impedance mismatch during the propagation of signals, which leads to signal reflection. Therefore, to potentially overcome this disadvantage, this work endeavors to establish the analytical model of the vertical interconnects for improving the impedance matching design. The key approach is to use the method of image charges for analyzing the substrate parasitic capacitance between the signal pin and grounding pins of the vertical interconnect. The proposed physical models are capable of predicting accurately the changes in characteristic impedance of various grounding pin arrangements in the vertical interconnect, and based on the prediction results the optimal impedance-matching design can be found. In this work, two types of vertical interconnects, through-silicon via (TSV) and pogo pin, are compared for discussion. Two physical models, one for single-ended signaling and the other for differential signaling, are developed to analyze how changes in TSV pitch-to-diameter ratio affect the characteristic impedance. Moreover, the same physical models are utilized to predict the changes in characteristic impedance caused by the alteration in the substrate parasitic capacitance between signal pin and grounding pins, under the circumstance that the information through the pogo pins is transmitted by single-ended signals with four different types of symmetric grounding architecture. The experiment in this work aims to improve the traditional coplanar probe stations used for measuring vertical interconnects. Traditionally, to extract the frequency response of the vertical interconnects under test, complex de-embedding techniques are required to calibrate out the parasitic effects of the test vehicle. However, the effective calibration bandwidth is limited. In response to this disadvantage, this work develops a double-sided probe station and calibrates the station with the help of a zero-delay thru. This setup can avoid the complex de-embedding process to measure the high frequency electrical properties of vertical interconnects in a more direct, accurate, and rapid manner. Compared to traditional means, the proposed method significantly enhances the measurement bandwidth. Finally, comparisons of S-parameters among the modeled, EM-simulated and measured results for the TSV and pogo pin structures are obtained. The comparisons demonstrate very good agreement, thereby verifying the proposed physical modeling methods for the vertical interconnects over a wide frequency range. |
| 抄録(英) | The advantages of vertical interconnects include superior electrical transmissions for stacked dies, higher I/O density, and heterogeneous integration. Despite the shorter physical length and superior electrical properties of the vertical interconnects, the arrangement of corresponding grounding pins drastically affects the characteristic impedance, resulting in impedance mismatch during the propagation of signals, which leads to signal reflection. Therefore, to potentially overcome this disadvantage, this work endeavors to establish the analytical model of the vertical interconnects for improving the impedance matching design. The key approach is to use the method of image charges for analyzing the substrate parasitic capacitance between the signal pin and grounding pins of the vertical interconnect. The proposed physical models are capable of predicting accurately the changes in characteristic impedance of various grounding pin arrangements in the vertical interconnect, and based on the prediction results the optimal impedance-matching design can be found. In this work, two types of vertical interconnects, through-silicon via (TSV) and pogo pin, are compared for discussion. Two physical models, one for single-ended signaling and the other for differential signaling, are developed to analyze how changes in TSV pitch-to-diameter ratio affect the characteristic impedance. Moreover, the same physical models are utilized to predict the changes in characteristic impedance caused by the alteration in the substrate parasitic capacitance between signal pin and grounding pins, under the circumstance that the information through the pogo pins is transmitted by single-ended signals with four different types of symmetric grounding architecture. The experiment in this work aims to improve the traditional coplanar probe stations used for measuring vertical interconnects. Traditionally, to extract the frequency response of the vertical interconnects under test, complex de-embedding techniques are required to calibrate out the parasitic effects of the test vehicle. However, the effective calibration bandwidth is limited. In response to this disadvantage, this work develops a double-sided probe station and calibrates the station with the help of a zero-delay thru. This setup can avoid the complex de-embedding process to measure the high frequency electrical properties of vertical interconnects in a more direct, accurate, and rapid manner. Compared to traditional means, the proposed method significantly enhances the measurement bandwidth. Finally, comparisons of S-parameters among the modeled, EM-simulated and measured results for the TSV and pogo pin structures are obtained. The comparisons demonstrate very good agreement, thereby verifying the proposed physical modeling methods for the vertical interconnects over a wide frequency range. |
| キーワード(和) | Vertical interconnect / through-silicon via / pogo pin / method of image charges / broadband physical model / double-sided probing system |
| キーワード(英) | Vertical interconnect / through-silicon via / pogo pin / method of image charges / broadband physical model / double-sided probing system |
| 資料番号 | EMCJ2016-35 |
| 発行日 | 2016-05-26 (EMCJ) |
| 研究会情報 | |
| 研究会 | EMCJ / IEE-EMC / IEE-MAG |
|---|---|
| 開催期間 | 2016/6/2(から2日開催) |
| 開催地（和） | NTU (台湾) |
| 開催地（英） | NTU, Taiwan |
| テーマ（和） | EMC Joint Workshop, 2016, Taipei |
| テーマ（英） | EMC Joint Workshop, 2016, Taipei |
| 委員長氏名（和） | 曽根 秀昭(東北大) / 川又 憲(東北学院大) / 山口 正洋(東北大) |
| 委員長氏名（英） | Hideaki Sone(Tohoku Univ.) / Ken Kawamata(Tohoku-gakuin Univ.) / Masahiro Yamaguchi(Tohoku Univ.) |
| 副委員長氏名（和） | 和田 修己(京大) |
| 副委員長氏名（英） | Osami Wada(Kyoto Univ.) |
| 幹事氏名（和） | 森岡 健浩(産総研) / 大坂 英樹(日立オートモティブシステムズ) / 牛尾 知雄(阪大) / 関口 秀紀(海技研) / 小原 学(明治大) |
| 幹事氏名（英） | Takehiro Morioka(AIST) / Hideki Osaka(Hitachi Automotive Systems) / Tomoo Ushio(Osaka Univ.) / Hidenori Sekiguchi(NMRI) / Gaku Obara(Meji Univ.) |
| 幹事補佐氏名（和） | 萓野 良樹(電通大) / 勝部 勇作(日立) / 佐々木 智江(パナソニック) / 林 優一(東北学院大) / 山田 啓壽(東芝) |
| 幹事補佐氏名（英） | Yoshiki Kayano(Univ. of Electro-Comm.) / Yusaku Katsube(Hitachi) / Chie Sasaki(Panasonic) / Yu-ichi Hayashi(Tohoku-gakuin Univ.) / Keiju Yamada(Toshiba Co.) |
| 講演論文情報詳細 | |
| 申込み研究会 | Technical Committee on Electromagnetic Compatibility / Technical Meeting on Electromagnetic Compatibility / Technical Meeting on Magnetics |
|---|---|
| 本文の言語 | ENG |
| タイトル（和） | |
| サブタイトル（和） | |
| タイトル（英） | [Invited Talk] Modeling and Measuring Vertical Interconnects with Impedance Control Over a Wide Frequency Range |
| サブタイトル（和） | |
| キーワード(1)（和/英） | Vertical interconnect / Vertical interconnect |
| キーワード(2)（和/英） | through-silicon via / through-silicon via |
| キーワード(3)（和/英） | pogo pin / pogo pin |
| キーワード(4)（和/英） | method of image charges / method of image charges |
| キーワード(5)（和/英） | broadband physical model / broadband physical model |
| キーワード(6)（和/英） | double-sided probing system / double-sided probing system |
| 第 1 著者 氏名（和/英） | Kuan-Chung Lu / Kuan-Chung Lu |
| 第 1 著者 所属（和/英） | National Sun Yat-sen University(略称：National Sun Yat-sen Univ.) National Sun Yat-sen University(略称：National Sun Yat-sen Univ.) |
| 第 2 著者 氏名（和/英） | Tzyy-Sheng Horng / Tzyy-Sheng Horng |
| 第 2 著者 所属（和/英） | National Sun Yat-sen University(略称：National Sun Yat-sen Univ.) National Sun Yat-sen University(略称：National Sun Yat-sen Univ.) |
| 発表年月日 | 2016-06-02 |
| 資料番号 | EMCJ2016-35 |
| 巻番号（vol） | vol.116 |
| 号番号（no） | EMCJ-72 |
| ページ範囲 | pp.57-62(EMCJ), |
| ページ数 | 6 |
| 発行日 | 2016-05-26 (EMCJ) |