| Presentation | 2016-06-10 FPGA implementation of Autoencoders for hw/sw complex system Suzuki Akihiro, Morie Takashi, Tamukoh Hakaru, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, we propose a digital circuit design of Autoencoders (AE) and its Field Programmable Gate Array (FPGA) implementation. The proposed digital circuit of AEs has circuit parameters and a common interface to be considered as an object in the system. A combination of FPGA and software for AEs can realize a low power consumption system which can process flexibly in real time. Experimental results show that the proposed circuits work as an AE and the combination of the circuits construct a stacked AE. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Deep Learning / Autoencoders / FPGA / hardware / Shared Synapse Architecture |
| Paper # | SIS2016-13 |
| Date of Issue | 2016-06-02 (SIS) |
| Conference Information | |
| Committee | SIS |
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| Conference Date | 2016/6/9(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kushiro Tourism and Convention cent. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Smart Personal Systems, etc. |
| Chair | Hirokazu Tanaka(Hiroshima City Univ.) |
| Vice Chair | Takayuki Nakachi(NTT) / Noriaki Suetake(Yamaguchi Univ.) |
| Secretary | Takayuki Nakachi(Toshiba) / Noriaki Suetake(Kanagawa Inst. of Tech.) |
| Assistant | Hakaru Tamukoh(Kyushu Inst. of Tech.) / Masaaki Fujiyoshi(Tokyo Metropolitan Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Smart Info-Media Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA implementation of Autoencoders for hw/sw complex system |
| Sub Title (in English) | |
| Keyword(1) | Deep Learning |
| Keyword(2) | Autoencoders |
| Keyword(3) | FPGA |
| Keyword(4) | hardware |
| Keyword(5) | Shared Synapse Architecture |
| 1st Author's Name | Suzuki Akihiro |
| 1st Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 2nd Author's Name | Morie Takashi |
| 2nd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| 3rd Author's Name | Tamukoh Hakaru |
| 3rd Author's Affiliation | Kyushu Institute of Technology(Kyutech) |
| Date | 2016-06-10 |
| Paper # | SIS2016-13 |
| Volume (vol) | vol.116 |
| Number (no) | SIS-81 |
| Page | pp.pp.65-68(SIS), |
| #Pages | 4 |
| Date of Issue | 2016-06-02 (SIS) |