| Presentation | 2016-06-17 A Study on Fault Tolerant Features of Asynchronous Circuits using Voted-enable Latches Masashi Imai, Tomohiro Yoneda, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A bit flip caused by voltage fluctuation, soft errors, and hardware Trojans becomes one of serious issues in the modern computer systems. In latch-based asynchronous circuits, it is relatively difficult to tolerate a bit flip since its enable signal is usually implemented using a single-wire, whose capacitance is small. In this paper, one idea to tolerate the bit flip in the latch-based asynchronous circuits is proposed. A new voted-enable D-latch circuitry is presented and its evaluation results are shown using the 130nm process technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Soft error / Hardware Trojan / Asynchronous circuits / Latch-based circuits / 2-phase handshaking protocol |
| Paper # | CAS2016-33,VLD2016-39,SIP2016-67,MSS2016-33 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | VLD / CAS / MSS / SIP |
|---|---|
| Conference Date | 2016/6/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hirosaki Shiritsu Kanko-kan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System, signal processing and related topics |
| Chair | Takashi Takenana(NEC) / Toshihiko Takahashi(Niigata Univ.) / Satoshi Yamane(Kanazawa Univ.) / Makoto Nakashizuka(Chiba Inst. of Tech.) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Mitsuru Hiraki(Renesas) / Morikazu Nakamura(Univ. of Ryukyus) / Masahiro Okuda(Univ. of Kitakyushu) / Shogo Muramatsu(Niigata Univ.) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Mitsuru Hiraki(Hiroshima City Univ.) / Morikazu Nakamura(Tohoku Univ.) / Masahiro Okuda(Renesas) / Shogo Muramatsu(Yamaguchi Univ.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) / Toshihiro Tachibana(Shonan Inst. of Tech.) / Yohei Nakamura(Hitachi) / Hideki Kinjo(Okinawa Univ.) / Osamu Watanabe(Takushoku Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Circuits and Systems / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on Signal Processing |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on Fault Tolerant Features of Asynchronous Circuits using Voted-enable Latches |
| Sub Title (in English) | |
| Keyword(1) | Soft error |
| Keyword(2) | Hardware Trojan |
| Keyword(3) | Asynchronous circuits |
| Keyword(4) | Latch-based circuits |
| Keyword(5) | 2-phase handshaking protocol |
| 1st Author's Name | Masashi Imai |
| 1st Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 2nd Author's Name | Tomohiro Yoneda |
| 2nd Author's Affiliation | National Institute of Informatics(NII) |
| Date | 2016-06-17 |
| Paper # | CAS2016-33,VLD2016-39,SIP2016-67,MSS2016-33 |
| Volume (vol) | vol.116 |
| Number (no) | CAS-93,VLD-94,SIP-95,MSS-96 |
| Page | pp.pp.179-184(CAS), pp.179-184(VLD), pp.179-184(SIP), pp.179-184(MSS), |
| #Pages | 6 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |