| Presentation | 2016-06-17 An FPGA Implementation of Real-time Optical Flow Estimation Processor Yu Suzuki, Masato Ito, Satoshi Kanda, Tetsuya Matsumura, Kousuke Imamura, Yoshio Matsuda, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A real-time optical flow processor has been implemented using single FPGA chip. By introducing four effective methods, modified newton’s method, hierarchical SOR method, modified initial flow generation method, and optimization of overlap pixels, both reducing the hardware amount and improving the flow accuracy are accomplished. Also by introducing the pipeline structure to this processor, high through-put hardware implementation can be realized. Total LC amount and memory capacity of this processor are reduced about 8% and 16% respectively compared to previous our HOE processor. This processor performs WXGA 30-fps at 175.5MHz real-time optical flow processing with single FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Optical flow / HOE / Newton's method / SOR method / Processor |
| Paper # | CAS2016-21,VLD2016-27,SIP2016-55,MSS2016-21 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | VLD / CAS / MSS / SIP |
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| Conference Date | 2016/6/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hirosaki Shiritsu Kanko-kan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System, signal processing and related topics |
| Chair | Takashi Takenana(NEC) / Toshihiko Takahashi(Niigata Univ.) / Satoshi Yamane(Kanazawa Univ.) / Makoto Nakashizuka(Chiba Inst. of Tech.) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Mitsuru Hiraki(Renesas) / Morikazu Nakamura(Univ. of Ryukyus) / Masahiro Okuda(Univ. of Kitakyushu) / Shogo Muramatsu(Niigata Univ.) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Mitsuru Hiraki(Hiroshima City Univ.) / Morikazu Nakamura(Tohoku Univ.) / Masahiro Okuda(Renesas) / Shogo Muramatsu(Yamaguchi Univ.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) / Toshihiro Tachibana(Shonan Inst. of Tech.) / Yohei Nakamura(Hitachi) / Hideki Kinjo(Okinawa Univ.) / Osamu Watanabe(Takushoku Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Circuits and Systems / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on Signal Processing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An FPGA Implementation of Real-time Optical Flow Estimation Processor |
| Sub Title (in English) | |
| Keyword(1) | Optical flow |
| Keyword(2) | HOE |
| Keyword(3) | Newton's method |
| Keyword(4) | SOR method |
| Keyword(5) | Processor |
| 1st Author's Name | Yu Suzuki |
| 1st Author's Affiliation | Nihon University(Nihon Univ.) |
| 2nd Author's Name | Masato Ito |
| 2nd Author's Affiliation | Nihon University(Nihon Univ.) |
| 3rd Author's Name | Satoshi Kanda |
| 3rd Author's Affiliation | Nihon University(Nihon Univ.) |
| 4th Author's Name | Tetsuya Matsumura |
| 4th Author's Affiliation | Nihon University(Nihon Univ.) |
| 5th Author's Name | Kousuke Imamura |
| 5th Author's Affiliation | Kanazawa University(Kanazawa Univ.) |
| 6th Author's Name | Yoshio Matsuda |
| 6th Author's Affiliation | Kanazawa University(Kanazawa Univ.) |
| Date | 2016-06-17 |
| Paper # | CAS2016-21,VLD2016-27,SIP2016-55,MSS2016-21 |
| Volume (vol) | vol.116 |
| Number (no) | CAS-93,VLD-94,SIP-95,MSS-96 |
| Page | pp.pp.115-120(CAS), pp.115-120(VLD), pp.115-120(SIP), pp.115-120(MSS), |
| #Pages | 6 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |