| Presentation | 2016-06-16 Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient Conrad JinYong Moore, Amir Masoud Gharehbaghi, Masahiro Fujita, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As fabricated circuitry gets larger and denser, modern industrial ATPG techniques which focus on the detection of single faults become more likely to overlook multiple (simultaneous) faults. Although there are exponentially more multiple faults than single faults, previous works have shown that given an initial set of test patterns for single faults, relatively few additional tests are required in order to cover all multiple faults. The exact situations in which test patterns generated by ATPG for single stuck-at (SSA) faults do not detect multiple stuck-at (MSA) faults will be examined. This will be done by presenting proofs which show the conditions that need to be met such that ATPG for single faults can cover all multiple faults. An analysis is then performed to determine the exact conditions that, when removed from the circuit, violate the assumption that ATPG for single faults will detect all multiple faults. Finally, our proposed ATPG algorithm will be explained. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Automatic Test Pattern Generation / Double Fault / Single Fault / Combinational Logic |
| Paper # | CAS2016-3,VLD2016-9,SIP2016-37,MSS2016-3 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | VLD / CAS / MSS / SIP |
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| Conference Date | 2016/6/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hirosaki Shiritsu Kanko-kan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System, signal processing and related topics |
| Chair | Takashi Takenana(NEC) / Toshihiko Takahashi(Niigata Univ.) / Satoshi Yamane(Kanazawa Univ.) / Makoto Nakashizuka(Chiba Inst. of Tech.) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Mitsuru Hiraki(Renesas) / Morikazu Nakamura(Univ. of Ryukyus) / Masahiro Okuda(Univ. of Kitakyushu) / Shogo Muramatsu(Niigata Univ.) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Mitsuru Hiraki(Hiroshima City Univ.) / Morikazu Nakamura(Tohoku Univ.) / Masahiro Okuda(Renesas) / Shogo Muramatsu(Yamaguchi Univ.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) / Toshihiro Tachibana(Shonan Inst. of Tech.) / Yohei Nakamura(Hitachi) / Hideki Kinjo(Okinawa Univ.) / Osamu Watanabe(Takushoku Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Circuits and Systems / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on Signal Processing |
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| Language | ENG-JTITLE |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient |
| Sub Title (in English) | |
| Keyword(1) | Automatic Test Pattern Generation |
| Keyword(2) | Double Fault |
| Keyword(3) | Single Fault |
| Keyword(4) | Combinational Logic |
| Keyword(5) | |
| 1st Author's Name | Conrad JinYong Moore |
| 1st Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 2nd Author's Name | Amir Masoud Gharehbaghi |
| 2nd Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| 3rd Author's Name | Masahiro Fujita |
| 3rd Author's Affiliation | The University of Tokyo(Univ. of Tokyo) |
| Date | 2016-06-16 |
| Paper # | CAS2016-3,VLD2016-9,SIP2016-37,MSS2016-3 |
| Volume (vol) | vol.116 |
| Number (no) | CAS-93,VLD-94,SIP-95,MSS-96 |
| Page | pp.pp.13-18(CAS), pp.13-18(VLD), pp.13-18(SIP), pp.13-18(MSS), |
| #Pages | 6 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |