| Presentation | 2016-06-17 Clock Distribution Network with Multiple Source Buffers for Stacked Chips Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, we present a method to reduce clock skew among stacked chips by a clock distribution network with multiple source buffers (MSB CDN). The propagation delays to all chips that need a clock signal are tuned only in the chip with a clock source. The adjustment is done in accordance with the size and number of buffers. Receivers in the same conditions are placed on each chip. The output signals of the receivers are subjected to waveform shaping. In this way, the delays and slews are unified. The proposed method has the advantage that all the chips except for the chip with a clock source can be designed by using a conventional method such as buffered clock tree synthesis (CTS). The experimental results demonstrate that the proposed method can reduce clock skew. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Clock Distribution Network (CDN) / 3D IC / Clock Skew / Through Silicon Vias (TSVs) |
| Paper # | CAS2016-31,VLD2016-37,SIP2016-65,MSS2016-31 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | VLD / CAS / MSS / SIP |
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| Conference Date | 2016/6/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hirosaki Shiritsu Kanko-kan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System, signal processing and related topics |
| Chair | Takashi Takenana(NEC) / Toshihiko Takahashi(Niigata Univ.) / Satoshi Yamane(Kanazawa Univ.) / Makoto Nakashizuka(Chiba Inst. of Tech.) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Mitsuru Hiraki(Renesas) / Morikazu Nakamura(Univ. of Ryukyus) / Masahiro Okuda(Univ. of Kitakyushu) / Shogo Muramatsu(Niigata Univ.) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Mitsuru Hiraki(Hiroshima City Univ.) / Morikazu Nakamura(Tohoku Univ.) / Masahiro Okuda(Renesas) / Shogo Muramatsu(Yamaguchi Univ.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) / Toshihiro Tachibana(Shonan Inst. of Tech.) / Yohei Nakamura(Hitachi) / Hideki Kinjo(Okinawa Univ.) / Osamu Watanabe(Takushoku Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Circuits and Systems / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on Signal Processing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Clock Distribution Network with Multiple Source Buffers for Stacked Chips |
| Sub Title (in English) | |
| Keyword(1) | Clock Distribution Network (CDN) |
| Keyword(2) | 3D IC |
| Keyword(3) | Clock Skew |
| Keyword(4) | Through Silicon Vias (TSVs) |
| 1st Author's Name | Nanako Niioka |
| 1st Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 2nd Author's Name | Masashi Imai |
| 2nd Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 3rd Author's Name | Kaoru Furumi |
| 3rd Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| 4th Author's Name | Atsushi Kurokawa |
| 4th Author's Affiliation | Hirosaki University(Hirosaki Univ.) |
| Date | 2016-06-17 |
| Paper # | CAS2016-31,VLD2016-37,SIP2016-65,MSS2016-31 |
| Volume (vol) | vol.116 |
| Number (no) | CAS-93,VLD-94,SIP-95,MSS-96 |
| Page | pp.pp.167-172(CAS), pp.167-172(VLD), pp.167-172(SIP), pp.167-172(MSS), |
| #Pages | 6 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |