| Presentation | 2016-06-17 Line selection to reduce store-energy in MTJ-based non-volatile caches Takamasa Fukasawa, Kimiyoshi Usami, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | There is a technique of power gating for reducing the energy consumption of the cache. The technique is a combination of power gating to reduce the leakage power and Non-volatile element(MTJ). However, there is a problem that energy consumption increases by writing on MTJ in entire cache lines. Therefore, we propose a method to select lines to store data in MTJ in descending order of the number of accesses. We show that energy is reduced by performing the proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Power Gating / MTJ / cache |
| Paper # | CAS2016-18,VLD2016-24,SIP2016-52,MSS2016-18 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |
| Conference Information | |
| Committee | VLD / CAS / MSS / SIP |
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| Conference Date | 2016/6/16(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hirosaki Shiritsu Kanko-kan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System, signal processing and related topics |
| Chair | Takashi Takenana(NEC) / Toshihiko Takahashi(Niigata Univ.) / Satoshi Yamane(Kanazawa Univ.) / Makoto Nakashizuka(Chiba Inst. of Tech.) |
| Vice Chair | Hiroyuki Ochi(Ritsumeikan Univ.) / Mitsuru Hiraki(Renesas) / Morikazu Nakamura(Univ. of Ryukyus) / Masahiro Okuda(Univ. of Kitakyushu) / Shogo Muramatsu(Niigata Univ.) |
| Secretary | Hiroyuki Ochi(Fujitsu Labs.) / Mitsuru Hiraki(Hiroshima City Univ.) / Morikazu Nakamura(Tohoku Univ.) / Masahiro Okuda(Renesas) / Shogo Muramatsu(Yamaguchi Univ.) |
| Assistant | Parizy Matthieu(Fujitsu Labs.) / Toshihiro Tachibana(Shonan Inst. of Tech.) / Yohei Nakamura(Hitachi) / Hideki Kinjo(Okinawa Univ.) / Osamu Watanabe(Takushoku Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Circuits and Systems / Technical Committee on Mathematical Systems Science and its applications / Technical Committee on Signal Processing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Line selection to reduce store-energy in MTJ-based non-volatile caches |
| Sub Title (in English) | |
| Keyword(1) | Power Gating |
| Keyword(2) | MTJ |
| Keyword(3) | cache |
| 1st Author's Name | Takamasa Fukasawa |
| 1st Author's Affiliation | Shibaura Institute of Technology(SIT) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology(SIT) |
| Date | 2016-06-17 |
| Paper # | CAS2016-18,VLD2016-24,SIP2016-52,MSS2016-18 |
| Volume (vol) | vol.116 |
| Number (no) | CAS-93,VLD-94,SIP-95,MSS-96 |
| Page | pp.pp.97-102(CAS), pp.97-102(VLD), pp.97-102(SIP), pp.97-102(MSS), |
| #Pages | 6 |
| Date of Issue | 2016-06-09 (CAS, VLD, SIP, MSS) |