| Presentation | 2016-05-21 A Study on Synaptic Weight Resolution in Hardware Implementation of Deep Neural Network Shouta Kurihara, Satoshi Moriya, Hisanao Akima, Masao Sakuraba, Shigeo Sato, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Deep learning implemented on a multi-layered network is one of the machine learning methods. The reason why deep learning attracts attention is the fact that it has high performance in image and speech recognition in comparison with conventional methods. Recently the hardware implementation of deep neural network has been studied actively, and one of the main factors limit the degree of integration is the hardware cost of synaptic weight memories. Therefore,in this report we study about the relation between the bit width of synaptic weights and learning performance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Deep Learning / Neural Network / Hardware / Synaptic Weight |
| Paper # | NC2016-5 |
| Date of Issue | 2016-05-14 (NC) |
| Conference Information | |
| Committee | MBE / NC |
|---|---|
| Conference Date | 2016/5/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | University of Toyama |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Tetsuo Kobayashi(Kyoto Univ.) / Toshimichi Saito(Hosei Univ.) |
| Vice Chair | Yutaka Fukuoka(Kogakuin Univ.) / Shigeo Sato(Tohoku Univ.) |
| Secretary | Yutaka Fukuoka(akita noken) / Shigeo Sato(Kogakuin Univ.) |
| Assistant | Takenori Oida(Kyoto Univ.) / Ryota Horie(Shibaura Inst. of Tech.) / Hiroyuki Kanbara(Tokyo Inst. of Tech.) / Hisanao Akima(Tohoku Univ.) |
| Paper Information | |
| Registration To | Technical Committee on ME and Bio Cybernetics / Technical Committee on Neurocomputing |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study on Synaptic Weight Resolution in Hardware Implementation of Deep Neural Network |
| Sub Title (in English) | |
| Keyword(1) | Deep Learning |
| Keyword(2) | Neural Network |
| Keyword(3) | Hardware |
| Keyword(4) | Synaptic Weight |
| 1st Author's Name | Shouta Kurihara |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Satoshi Moriya |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Hisanao Akima |
| 3rd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 4th Author's Name | Masao Sakuraba |
| 4th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 5th Author's Name | Shigeo Sato |
| 5th Author's Affiliation | Tohoku University(Tohoku Univ.) |
| Date | 2016-05-21 |
| Paper # | NC2016-5 |
| Volume (vol) | vol.116 |
| Number (no) | NC-59 |
| Page | pp.pp.23-28(NC), |
| #Pages | 6 |
| Date of Issue | 2016-05-14 (NC) |