Presentation 2016-05-19
Simulation of error-correcting code using LDPC code with Sum-Product method for a single-dot pattern method
Kitahiro Kaneda, Yasuyuki Anezaki, Keiichi Iwamura, Isao Echizen,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) We have proposed a single dot information hiding method for printed matter. In this paper, we try to apply LDPC error correction code into a single dot information hiding method for improving its accuracy. As a result we show no error with 38880bit information capacity at printed character density 17% A4 document.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Single Dot Information Hiding Method / LDPC Error Correction Code / Sum-Product Decode
Paper # IT2016-7,EMM2016-7
Date of Issue 2016-05-12 (IT, EMM)

Conference Information
Committee IT / EMM
Conference Date 2016/5/19(2days)
Place (in Japanese) (See Japanese page)
Place (in English) Otaru Economic Center
Topics (in Japanese) (See Japanese page)
Topics (in English) Information Security, Information Theory, Information Hiding, etc.
Chair Yasutada Oohama(Univ. of Electro-Comm.) / Akinori Ito(Tohoku Univ.)
Vice Chair Tadashi Wadayama(Nagoya Inst. of Tech.) / Masashi Unoki(JAIST) / Masaki Kawamura(Yamaguchi Univ.)
Secretary Tadashi Wadayama(Univ. of Electro-Comm.) / Masashi Unoki(Wakayama Univ.) / Masaki Kawamura(Univ. of Electro-Comm.)
Assistant Takuya Kusaka(Okayama Univ.) / Motoi Iwata(Osaka Pref. Univ.) / Kazuhiro Kohno(Kansai Univ.)

Paper Information
Registration To Technical Committee on Information Theory / Technical Committee on Enriched MultiMedia
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Simulation of error-correcting code using LDPC code with Sum-Product method for a single-dot pattern method
Sub Title (in English)
Keyword(1) Single Dot Information Hiding Method
Keyword(2) LDPC Error Correction Code
Keyword(3) Sum-Product Decode
Keyword(4)
Keyword(5)
1st Author's Name Kitahiro Kaneda
1st Author's Affiliation Osaka Prefecture University(Osaka Prefecture Univ.)
2nd Author's Name Yasuyuki Anezaki
2nd Author's Affiliation Tokyo University of Science(TUS)
3rd Author's Name Keiichi Iwamura
3rd Author's Affiliation Tokyo University of Science(TUS)
4th Author's Name Isao Echizen
4th Author's Affiliation National Institute of Informatics(NII)
Date 2016-05-19
Paper # IT2016-7,EMM2016-7
Volume (vol) vol.116
Number (no) IT-33,EMM-34
Page pp.pp.37-42(IT), pp.37-42(EMM),
#Pages 6
Date of Issue 2016-05-12 (IT, EMM)