講演名 | 2016-05-11 MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA Xushen Han(早大), Dajiang Zhou(早大), Shinji Kimura(早大), |
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抄録(和) | Convolutional neural network has been paid so much attention in many intelligent applications especially image pattern recognition. Nowadays lots of high-throughput implementations are developed for acceleration of convolutional neural network, however, memory traffic has been the bottleneck if more resources are distributed on chip. In this paper we present MERP-CNN, a memory-efficient processor for both forward and backward propagation of convolutional neural networks. We implement our processor on Xilinx Vertex 7 FPGA platform. Our memory efficiency is 35.6% less than recent previous works. We also have a 279GFlops throughput for acceleration and not bad power performance. We take advantage of the multiboot specialty to keep top performance of our hardware resources. |
抄録(英) | Convolutional neural network has been paid so much attention in many intelligent applications especially image pattern recognition. Nowadays lots of high-throughput implementations are developed for acceleration of convolutional neural network, however, memory traffic has been the bottleneck if more resources are distributed on chip. In this paper we present MERP-CNN, a memory-efficient processor for both forward and backward propagation of convolutional neural networks. We implement our processor on Xilinx Vertex 7 FPGA platform. Our memory efficiency is 35.6% less than recent previous works. We also have a 279GFlops throughput for acceleration and not bad power performance. We take advantage of the multiboot specialty to keep top performance of our hardware resources. |
キーワード(和) | convolutional neural network / memory-efficient / multiboot |
キーワード(英) | convolutional neural network / memory-efficient / multiboot |
資料番号 | VLD2016-5 |
発行日 | 2016-05-04 (VLD) |
研究会情報 | |
研究会 | VLD / IPSJ-SLDM |
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開催期間 | 2016/5/11(から1日開催) |
開催地(和) | 北九州国際会議場 |
開催地(英) | Kitakyushu International Conference Center |
テーマ(和) | システム設計および一般 |
テーマ(英) | System Design, etc. |
委員長氏名(和) | 松永 裕介(九大) / 福井 正博(立命館大) |
委員長氏名(英) | Yusuke Matsunaga(Kyushu Univ.) / Masahiro Fukui(Ritsumeikan Univ.) |
副委員長氏名(和) | 竹中 崇(NEC) |
副委員長氏名(英) | Takashi Takenana(NEC) |
幹事氏名(和) | 冨山 宏之(立命館大) / 福田 大輔(富士通研) / 横山 昌生(シャープ) / 高島 康裕(北九州市大) / 西出 岳央(東芝) |
幹事氏名(英) | Hiroyuki Tomiyama(Ritsumeikan Univ.) / Daisuke Fukuda(Fujitsu Labs.) / Masao Yokoyama(Sharp) / Yasuhiro Takashima(Kitakyushu City Univ.) / Takeo Nishide(Toshiba) |
幹事補佐氏名(和) | 谷口 一徹(立命館大) |
幹事補佐氏名(英) | Ittetsu Taniguchi(Ritsumeikan Univ.) |
講演論文情報詳細 | |
申込み研究会 | Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology |
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本文の言語 | ENG |
タイトル(和) | |
サブタイトル(和) | |
タイトル(英) | MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA |
サブタイトル(和) | |
キーワード(1)(和/英) | convolutional neural network / convolutional neural network |
キーワード(2)(和/英) | memory-efficient / memory-efficient |
キーワード(3)(和/英) | multiboot / multiboot |
第 1 著者 氏名(和/英) | Xushen Han / Xushen Han |
第 1 著者 所属(和/英) | Waseda University(略称:早大) Waseda University(略称:Waseda Univ.) |
第 2 著者 氏名(和/英) | Dajiang Zhou / Dajiang Zhou |
第 2 著者 所属(和/英) | Waseda University(略称:早大) Waseda University(略称:Waseda Univ.) |
第 3 著者 氏名(和/英) | Shinji Kimura / Shinji Kimura |
第 3 著者 所属(和/英) | Waseda University(略称:早大) Waseda University(略称:Waseda Univ.) |
発表年月日 | 2016-05-11 |
資料番号 | VLD2016-5 |
巻番号(vol) | vol.116 |
号番号(no) | VLD-21 |
ページ範囲 | pp.47-52(VLD), |
ページ数 | 6 |
発行日 | 2016-05-04 (VLD) |