| Presentation | 2016-05-11 MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA Xushen Han, Dajiang Zhou, Shinji Kimura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Convolutional neural network has been paid so much attention in many intelligent applications especially image pattern recognition. Nowadays lots of high-throughput implementations are developed for acceleration of convolutional neural network, however, memory traffic has been the bottleneck if more resources are distributed on chip. In this paper we present MERP-CNN, a memory-efficient processor for both forward and backward propagation of convolutional neural networks. We implement our processor on Xilinx Vertex 7 FPGA platform. Our memory efficiency is 35.6% less than recent previous works. We also have a 279GFlops throughput for acceleration and not bad power performance. We take advantage of the multiboot specialty to keep top performance of our hardware resources. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | convolutional neural network / memory-efficient / multiboot |
| Paper # | VLD2016-5 |
| Date of Issue | 2016-05-04 (VLD) |
| Conference Information | |
| Committee | VLD / IPSJ-SLDM |
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| Conference Date | 2016/5/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Masahiro Fukui(Ritsumeikan Univ.) |
| Vice Chair | Takashi Takenana(NEC) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / (Fujitsu Labs.) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Special Interest Group on System and LSI Design Methodology |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA |
| Sub Title (in English) | |
| Keyword(1) | convolutional neural network |
| Keyword(2) | memory-efficient |
| Keyword(3) | multiboot |
| 1st Author's Name | Xushen Han |
| 1st Author's Affiliation | Waseda University(Waseda Univ.) |
| 2nd Author's Name | Dajiang Zhou |
| 2nd Author's Affiliation | Waseda University(Waseda Univ.) |
| 3rd Author's Name | Shinji Kimura |
| 3rd Author's Affiliation | Waseda University(Waseda Univ.) |
| Date | 2016-05-11 |
| Paper # | VLD2016-5 |
| Volume (vol) | vol.116 |
| Number (no) | VLD-21 |
| Page | pp.pp.47-52(VLD), |
| #Pages | 6 |
| Date of Issue | 2016-05-04 (VLD) |