Presentation 2016-05-20
A Sound Field Visualizer with Java-based High Level Synthesis Tool and CoRAM Architecture Synthesis Framework
Daichi Teruya, Daichi Miyazaki, Hironori Nakajo,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Currently the number of devices which uses multiple sensors has been increasing due to recent significant interest on the keyword as ‘Internet of Things.’In such a device, processing power is insufficient to handle a large amount of sensor data. In order to reinforce processing power, hardware acceleration using an FPGA is expected to be a promising technology. However, designing an acceleration circuit seems to bring a significant design complexity. In this report, we introduce an implementation of an FPGA acceleration in a sound-field visualizer with a Beamforming method. In this implementation, we adopt a Java based high level synthesis tool called Synthesijer as well as the framework of CoRAM architecture synthesis to implement portable circuits. We have achieved a short term implementation using these tools in an efficient testing environment.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / CoRAM / HLS
Paper # RECONF2016-20
Date of Issue 2016-05-12 (RECONF)

Conference Information
Committee RECONF
Conference Date 2016/5/19(2days)
Place (in Japanese) (See Japanese page)
Place (in English) FUJITSU LAB.
Topics (in Japanese) (See Japanese page)
Topics (in English) Reconfigurable Systems, etc.
Chair Minoru Watanabe(Shizuoka Univ.)
Vice Chair Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.)
Secretary Masato Motomura(Toshiba) / Yuichiro Shibata(Univ. of Tsukuba)
Assistant Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan)

Paper Information
Registration To Technical Committee on Reconfigurable Systems
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Sound Field Visualizer with Java-based High Level Synthesis Tool and CoRAM Architecture Synthesis Framework
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) CoRAM
Keyword(3) HLS
1st Author's Name Daichi Teruya
1st Author's Affiliation Tokyo University of Agriculture and Tecnology(TUAT)
2nd Author's Name Daichi Miyazaki
2nd Author's Affiliation Tokyo University of Agriculture and Tecnology(TUAT)
3rd Author's Name Hironori Nakajo
3rd Author's Affiliation Tokyo University of Agriculture and Tecnology(TUAT)
Date 2016-05-20
Paper # RECONF2016-20
Volume (vol) vol.116
Number (no) RECONF-53
Page pp.pp.97-102(RECONF),
#Pages 6
Date of Issue 2016-05-12 (RECONF)