Presentation 2016-05-19
Efficiency Execution of Split Circuit in a Scalable Hardware System by Signal Compression
Yoshio Murata, Hironari Yoshiuchi, Hironori Nakajo,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / circuit partition / lossless compression
Paper # RECONF2016-8
Date of Issue 2016-05-12 (RECONF)

Conference Information
Committee RECONF
Conference Date 2016/5/19(2days)
Place (in Japanese) (See Japanese page)
Place (in English) FUJITSU LAB.
Topics (in Japanese) (See Japanese page)
Topics (in English) Reconfigurable Systems, etc.
Chair Minoru Watanabe(Shizuoka Univ.)
Vice Chair Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.)
Secretary Masato Motomura(Toshiba) / Yuichiro Shibata(Univ. of Tsukuba)
Assistant Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan)

Paper Information
Registration To Technical Committee on Reconfigurable Systems
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Efficiency Execution of Split Circuit in a Scalable Hardware System by Signal Compression
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) circuit partition
Keyword(3) lossless compression
1st Author's Name Yoshio Murata
1st Author's Affiliation Tokyo University of Agriculture and Technology(TUAT)
2nd Author's Name Hironari Yoshiuchi
2nd Author's Affiliation Tokyo University of Agriculture and Technology(TUAT)
3rd Author's Name Hironori Nakajo
3rd Author's Affiliation Tokyo University of Agriculture and Technology(TUAT)
Date 2016-05-19
Paper # RECONF2016-8
Volume (vol) vol.116
Number (no) RECONF-53
Page pp.pp.35-40(RECONF),
#Pages 6
Date of Issue 2016-05-12 (RECONF)