| Presentation | 2016-04-21 Parallel Implementation of Cipher on CPU/GPU for Programmable Optical Access Equipment Takahiro Suzuki, Sang-Yuep Kim, Jun-ichi Kani, Ken-Ichi Suzuki, Akihiro Otaka, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, NFV and SDN are attracting attention with the goal being enhanced networks efficiency. In access network, software implementation of functions of communications equipment is pursued for speeding service provision and CAPEX/OPEX reduction by commonalizing and integrated equipment of plural services. This paper proposes the programmable OLT; it performs OLT functions by software processing on general-purpose hardware. To accomplish the programmable OLT, the problem is to achieve requested throughput of access equipment on general-purpose hardware. We evaluated throughput of functions of PON system, modulation/demodulation signal processing, error correction and cipher, on simulator of many-core CPU and show a consider policy. In addition, cipher algorithm is implemented on CPU/GPU. The results show throughput of 1.12 Gbps with CTR-AES-128 and 1.13 Gbps with GCM-AES-128 on CPU. In addition, they show throughput of 5.37 Gbps with CTR-AES-128 and 914 Mbps with GCM-AES-128 on GPU. They show the feasibility of software implementation of 1-Gbps-class cipher processing. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Access network / NFV / Cipher / Parallelization / GPU |
| Paper # | CS2016-1 |
| Date of Issue | 2016-04-14 (CS) |
| Conference Information | |
| Committee | CS / CQ |
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| Conference Date | 2016/4/21(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | SDN (Software-Defined Networking), NFV（Network Functions. Virtualization）, Network Virtualization, Cloud, Service Quality, Contents Delivery, etc |
| Chair | Toshinori Tsuboi(Tokyo Univ. of Tech.) / Kyoko Yamori(Asahi Univ.) |
| Vice Chair | Tetsuya Yokotani(Kanazawa Inst. of Tech.) / Takanori Hayashi(NTT) / Hideyuki Shimonishi(NEC) |
| Secretary | Tetsuya Yokotani(Hiroshima City Univ.) / Takanori Hayashi(NTT) / Hideyuki Shimonishi(NEC) |
| Assistant | / Masahiro Yamamoto(OKI) / Bo GU(Waseda Univ.) / Hirantha Abeysekera(NTT) |
| Paper Information | |
| Registration To | Technical Committee on Communication Systems / Technical Committee on Communication Quality |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Parallel Implementation of Cipher on CPU/GPU for Programmable Optical Access Equipment |
| Sub Title (in English) | |
| Keyword(1) | Access network |
| Keyword(2) | NFV |
| Keyword(3) | Cipher |
| Keyword(4) | Parallelization |
| Keyword(5) | GPU |
| 1st Author's Name | Takahiro Suzuki |
| 1st Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| 2nd Author's Name | Sang-Yuep Kim |
| 2nd Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| 3rd Author's Name | Jun-ichi Kani |
| 3rd Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| 4th Author's Name | Ken-Ichi Suzuki |
| 4th Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| 5th Author's Name | Akihiro Otaka |
| 5th Author's Affiliation | Nippon Telegraph and Telephone Corporation(NTT) |
| Date | 2016-04-21 |
| Paper # | CS2016-1 |
| Volume (vol) | vol.116 |
| Number (no) | CS-9 |
| Page | pp.pp.1-6(CS), |
| #Pages | 6 |
| Date of Issue | 2016-04-14 (CS) |