| Presentation | 2016-03-25 A Study of the Dynamic Power Estimate Method for FPGA Accelerator Keisuke Fujimoto, Shinya Takamaeda, Yasuhiko Nakashima, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Power consumption estimation is essential for the FPGA accelerator-used high-performance computer system. However, the dynamic power consumption of FPGA cannot be estimated without direct tool measurement.Therefore, we proposed the estimation method based on the information of both state machine transition speed and the updating period of the registers.For an evaluation, We implemented two evaluation board.The first board capable of configuring the register count and updating period and the second board capable of configuring the state transition speed.Our evaluation validated that the dynamic power consumption is affected by all parameters, i.e., updating period and amount of the register, the transition speed of state machine and the duty ratio. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / FPGA accelerator / Dynamic power estimate |
| Paper # | CPSY2015-156,DC2015-110 |
| Date of Issue | 2016-03-17 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2016/3/24(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Fukue Bunka Hall/Rodou Fukushi Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2016 |
| Chair | Yasuhiko Nakashima(NAIST) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) |
| Vice Chair | Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Michiko Inoue(NAIST) |
| Secretary | Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Michiko Inoue(RTRI) / (Kyoto Sangyo Univ.) / (Sharp) / (Kitakyushu City Univ.) |
| Assistant | Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Study of the Dynamic Power Estimate Method for FPGA Accelerator |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | FPGA accelerator |
| Keyword(3) | Dynamic power estimate |
| 1st Author's Name | Keisuke Fujimoto |
| 1st Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 2nd Author's Name | Shinya Takamaeda |
| 2nd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 3rd Author's Name | Yasuhiko Nakashima |
| 3rd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| Date | 2016-03-25 |
| Paper # | CPSY2015-156,DC2015-110 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-518,DC-519 |
| Page | pp.pp.259-264(CPSY), pp.259-264(DC), |
| #Pages | 6 |
| Date of Issue | 2016-03-17 (CPSY, DC) |