| Presentation | 2016-03-25 Design Evaluation of Low-Latency Handshake Join on FPGA Masato Yoshimi, Yasin Oge, Celimuge Wu, Tsutomu Yoshinaga, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This work revisits the processing of sliding-window joins on FPGAs. In this paper, we propose an FPGA-based implementation of low-latency handshake join algorithm and present a detailed evaluation of the proposed design. The proposed design overcomes the limitation of the previous works by reducing the latency overhead. Our experiments show that the proposed low-latency handshake join hardware can achieve linear scalability with respect to the number of join cores without sacrificing latency (e.g., nearly 7 million tuples per second of throughput with less than a micro-second of latency). Evaluation results also indicate that the proposed design significantly outperforms the software-based approach in terms of both latency and throughput |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / query processing / data stream / sliding-window join / low-latency handshake join |
| Paper # | CPSY2015-155,DC2015-109 |
| Date of Issue | 2016-03-17 (CPSY, DC) |
| Conference Information | |
| Committee | CPSY / DC / IPSJ-SLDM / IPSJ-EMB / IPSJ-ARC |
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| Conference Date | 2016/3/24(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Fukue Bunka Hall/Rodou Fukushi Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2016 |
| Chair | Yasuhiko Nakashima(NAIST) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) |
| Vice Chair | Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Michiko Inoue(NAIST) |
| Secretary | Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) / Michiko Inoue(RTRI) / (Kyoto Sangyo Univ.) / (Sharp) / (Kitakyushu City Univ.) |
| Assistant | Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Computer Systems / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Special Interest Group on Embedded Systems / Special Interest Group on System Architecture |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Evaluation of Low-Latency Handshake Join on FPGA |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | query processing |
| Keyword(3) | data stream |
| Keyword(4) | sliding-window join |
| Keyword(5) | low-latency handshake join |
| 1st Author's Name | Masato Yoshimi |
| 1st Author's Affiliation | University of Electro-Communications(UEC) |
| 2nd Author's Name | Yasin Oge |
| 2nd Author's Affiliation | University of Electro-Communications(UEC) |
| 3rd Author's Name | Celimuge Wu |
| 3rd Author's Affiliation | University of Electro-Communications(UEC) |
| 4th Author's Name | Tsutomu Yoshinaga |
| 4th Author's Affiliation | University of Electro-Communications(UEC) |
| Date | 2016-03-25 |
| Paper # | CPSY2015-155,DC2015-109 |
| Volume (vol) | vol.115 |
| Number (no) | CPSY-518,DC-519 |
| Page | pp.pp.253-258(CPSY), pp.253-258(DC), |
| #Pages | 6 |
| Date of Issue | 2016-03-17 (CPSY, DC) |