| Presentation | 2016-03-10 A Multiplier Architecture for Finite Field of 254bit-Prime Square Order Based on Pipelined 32bit Montgomery Multipliers Yusuke Nagahama, Daisuke Fujimoto, Tsutomu Matsumoto, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Bilinear Pairing is a major tool to realize advanced cryptographic functionality such as searchable encryption, aggregate signature, proxy re-encryption, attribute-based and functional encryption. Pairing at 126bit security can be realized efficiently by using a BN curve over GF(p) with embedding degree 12, where p is a 254bit prime. Aiming at designing a superior hardware engine for the BN-curve based pairing computation including GF(p), GF(p^2), and GF(p^12) operations we propose a multiplier architecture for GF(p^2) based on pipelined 32bit Montgomery multipliers and evaluate the resultant performances. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Cryptographic Hardware Architecture / Finite Field Multiplier / Montgomery Multiplication / Pipeline Implementation / Pairing Cryptography |
| Paper # | IT2015-116,ISEC2015-75,WBS2015-99 |
| Date of Issue | 2016-03-03 (IT, ISEC, WBS) |
| Conference Information | |
| Committee | IT / ISEC / WBS |
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| Conference Date | 2016/3/10(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | The University of Electro-Communications |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | joint meeting of IT, ISEC, and WBS |
| Chair | Yasutada Oohama(Univ. of Electro-Comm.) / Yukiyasu Tsunoo(NEC) / Hiromasa Habuchi(Ibaraki Univ.) |
| Vice Chair | Tadashi Wadayama(Nagoya Inst. of Tech.) / Masahiro Mambo(Kanazawa Univ.) / Kazuto Ogawa(NHK) / Fumiaki Maehara(Waseda Univ.) / Minoru Okada(NAIST) |
| Secretary | Tadashi Wadayama(Univ. of Electro-Comm.) / Masahiro Mambo(Wakayama Univ.) / Kazuto Ogawa(AIST) / Fumiaki Maehara(Toshiba) / Minoru Okada(Univ. of Kitakyushu) |
| Assistant | Takuya Kusaka(Okayama Univ.) / Tetsuya Izu(Fujitsu Lab.) / Takaaki Mizuki(Tohoku Univ.) / Noritaka Yamashita(NEC) / Yusuke Kozawa(Tokyo Univ. of Science) / Akira Nakamura(Tokyo Univ. of Science) / Ryohei Nakamura(National Defense Academy) |
| Paper Information | |
| Registration To | Technical Committee on Information Theory / Technical Committee on Information Security / Technical Committee on Wideband System |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Multiplier Architecture for Finite Field of 254bit-Prime Square Order Based on Pipelined 32bit Montgomery Multipliers |
| Sub Title (in English) | |
| Keyword(1) | Cryptographic Hardware Architecture |
| Keyword(2) | Finite Field Multiplier |
| Keyword(3) | Montgomery Multiplication |
| Keyword(4) | Pipeline Implementation |
| Keyword(5) | Pairing Cryptography |
| 1st Author's Name | Yusuke Nagahama |
| 1st Author's Affiliation | Yokohama National University(YNU) |
| 2nd Author's Name | Daisuke Fujimoto |
| 2nd Author's Affiliation | Yokohama National University(YNU) |
| 3rd Author's Name | Tsutomu Matsumoto |
| 3rd Author's Affiliation | Yokohama National University(YNU) |
| Date | 2016-03-10 |
| Paper # | IT2015-116,ISEC2015-75,WBS2015-99 |
| Volume (vol) | vol.115 |
| Number (no) | IT-500,ISEC-501,WBS-502 |
| Page | pp.pp.95-100(IT), pp.95-100(ISEC), pp.95-100(WBS), |
| #Pages | 6 |
| Date of Issue | 2016-03-03 (IT, ISEC, WBS) |