| Presentation | 2016-03-11 A Performance Evaluation of Packet Processing Architectures for NFV Environment Shin Muramatsu, Ryota Kawashima, Hiroki Nakayama, Tsunemasa Hayashi, Hiroshi Matsuo, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The notion of Network Functions Virtualization (NFV) has been introduced into commercial networks for fast and flexible service deployment. Service chaining is a key technology to realize the NFV concept, however, current NFV implementation suffers performance problems because network functions are provided as software components on commodity IA servers. So far, various high-performance packet processing architectures such as Intel DPDK have been proposed, but there is no comprehensive study that evaluated the performance effect of these architectures and combinations of them. In this paper, we evaluate performance of various packet processing architectures (NAPI, netmap, and Intel DPDK) , virtual switches (Open vSwitch, VALE, and Lagopus) and virtual NIC back-ends (vhost-net and vhost-user), and discuss appropriate architectures for commercial NFV environment. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | NFV / Open vSwitch / Lagopus / VALE / netmap / Intel DPDK |
| Paper # | ICM2015-47 |
| Date of Issue | 2016-03-03 (ICM) |
| Conference Information | |
| Committee | ICM |
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| Conference Date | 2016/3/10(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Element Management, Management Functionalities, Operations and Management Technologies |
| Chair | Shingo Ata(Osaka City Univ.) |
| Vice Chair | Kiyohito Yoshihara(KDDI R&D Labs.) / Manabu Nakagawa(NTT Communications) |
| Secretary | Kiyohito Yoshihara(Hitachi) / Manabu Nakagawa(NEC) |
| Assistant | Masao Murata(Fujitsu) |
| Paper Information | |
| Registration To | Technical Committee on Information and Communication Management |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Performance Evaluation of Packet Processing Architectures for NFV Environment |
| Sub Title (in English) | |
| Keyword(1) | NFV |
| Keyword(2) | Open vSwitch |
| Keyword(3) | Lagopus |
| Keyword(4) | VALE |
| Keyword(5) | netmap |
| Keyword(6) | Intel DPDK |
| 1st Author's Name | Shin Muramatsu |
| 1st Author's Affiliation | Nagoya Institute of Technology(NIT) |
| 2nd Author's Name | Ryota Kawashima |
| 2nd Author's Affiliation | Nagoya Institute of Technology(NIT) |
| 3rd Author's Name | Hiroki Nakayama |
| 3rd Author's Affiliation | BOSCO Technologies, Inc.(BOSCO) |
| 4th Author's Name | Tsunemasa Hayashi |
| 4th Author's Affiliation | BOSCO Technologies, Inc.(BOSCO) |
| 5th Author's Name | Hiroshi Matsuo |
| 5th Author's Affiliation | Nagoya Institute of Technology(NIT) |
| Date | 2016-03-11 |
| Paper # | ICM2015-47 |
| Volume (vol) | vol.115 |
| Number (no) | ICM-507 |
| Page | pp.pp.31-36(ICM), |
| #Pages | 6 |
| Date of Issue | 2016-03-03 (ICM) |