Presentation 2016-03-01
A Screening Circuit for Intrusion Detection of High-Speed Networks and its FPGA Implementation
Hiroki Takaguchi, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # VLD2015-119
Date of Issue 2016-02-22 (VLD)

Conference Information
Committee VLD
Conference Date 2016/2/29(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Okinawa Seinen Kaikan
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Yusuke Matsunaga(Kyushu Univ.)
Vice Chair Takashi Takenana(NEC)
Secretary Takashi Takenana(Ritsumeikan Univ.)
Assistant Ittetsu Taniguchi(Ritsumeikan Univ.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Screening Circuit for Intrusion Detection of High-Speed Networks and its FPGA Implementation
Sub Title (in English)
Keyword(1)
1st Author's Name Hiroki Takaguchi
1st Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
2nd Author's Name Shin'ichi Wakabayashi
2nd Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
3rd Author's Name Shinobu Nagayama
3rd Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
4th Author's Name Masato Inagi
4th Author's Affiliation Hiroshima City University(Hiroshima City Univ.)
Date 2016-03-01
Paper # VLD2015-119
Volume (vol) vol.115
Number (no) VLD-465
Page pp.pp.49-54(VLD),
#Pages 6
Date of Issue 2016-02-22 (VLD)