| Presentation | 2016-03-01 Power Analysis Attack for Countermeasure with Check Circuit Yoshiya Ikezaki, Masaya Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The thread of side-channel attack against cryptgraphic circuit is pointed out. Side-channel attack is classified into two attack methods; fault analysis attack and power analysis attack. A fault analysis attack intentionally generates operation errors during the encryption processing, and obtains confidential information using pairs of an incorrect cryptogram and a correct one. A method using a check circuit was reported as a typical measure against a fault analysis attack. A power analysis attack uses the correlation between encryption processing and power consumption. However, there is no report of which a power analysis attack is applied to check circuit. Therefore, this study proposes a new power analysis method for AES with check circuit. Experiments using an actual device prove the validity of the proposed method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | AES / Power Analysis Attack / Check Circuit |
| Paper # | VLD2015-122 |
| Date of Issue | 2016-02-22 (VLD) |
| Conference Information | |
| Committee | VLD |
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| Conference Date | 2016/2/29(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Yusuke Matsunaga(Kyushu Univ.) |
| Vice Chair | Takashi Takenana(NEC) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power Analysis Attack for Countermeasure with Check Circuit |
| Sub Title (in English) | |
| Keyword(1) | AES |
| Keyword(2) | Power Analysis Attack |
| Keyword(3) | Check Circuit |
| 1st Author's Name | Yoshiya Ikezaki |
| 1st Author's Affiliation | Meijo University(Meijo Univ.) |
| 2nd Author's Name | Masaya Yoshikawa |
| 2nd Author's Affiliation | Meijo University(Meijo Univ.) |
| Date | 2016-03-01 |
| Paper # | VLD2015-122 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-465 |
| Page | pp.pp.67-72(VLD), |
| #Pages | 6 |
| Date of Issue | 2016-02-22 (VLD) |