Presentation 2016-02-17
Delay fault injection framework based on logic simulation with zero delay model
Shinji Kawasaki, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Fault injection is a technique to re-create faulty behavior of circuits and widely accepted method to evaluate soft error effects.This paper presents a delay fault injection framework to efficiently analyze circuit behavior with delay faults.The proposed framework is based on logic simulation with zero-delay model. Therefore, it is faster than traditional timing simulation with SDF back annotation.And this framework can be emulated in FPGAs. In that case, analysis become much faster than logic simulation.Experimental results show the effectiveness of the proposed method in terms of accuracy and speed-up for delay fault analysis.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) fault injection / timing simulation / FPGA
Paper # DC2015-90
Date of Issue 2016-02-10 (DC)

Conference Information
Committee DC
Conference Date 2016/2/17(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kikai-Shinko-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) VLSI Design and Test, etc.
Chair Nobuyasu Kanekawa(Hitachi)
Vice Chair Michiko Inoue(NAIST)
Secretary Michiko Inoue(RTRI)
Assistant

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Delay fault injection framework based on logic simulation with zero delay model
Sub Title (in English)
Keyword(1) fault injection
Keyword(2) timing simulation
Keyword(3) FPGA
1st Author's Name Shinji Kawasaki
1st Author's Affiliation Nara Institute of Science and Technology(NAIST)
2nd Author's Name Tomokazu Yoneda
2nd Author's Affiliation Nara Institute of Science and Technology(NAIST)
3rd Author's Name Yuta Yamato
3rd Author's Affiliation Nara Institute of Science and Technology(NAIST)
4th Author's Name Michiko Inoue
4th Author's Affiliation Nara Institute of Science and Technology(NAIST)
Date 2016-02-17
Paper # DC2015-90
Volume (vol) vol.115
Number (no) DC-449
Page pp.pp.25-30(DC),
#Pages 6
Date of Issue 2016-02-10 (DC)