| Presentation | 2016-02-17 Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Stochastic computing, which is a computational scheme with probabilities, is notable for its applicability to error tolerant applications. In this study, we discuss a dynamic share of consecutive bit sequences, which are called stochastic numbers, in order to accelerate stochastic computing. A basic idea of dynamic share of consecutive stochastic numbers has been presented. We consider the feasibility of this dynamic share of stochastic numbers, and then propose a hardware architecture for implementing this dynamic share. Moreover, based on discussion of area efficiency of the hardware, we propose an algorithm, which is called a selection method, to determine the length of bit sharing. Experimental results show that the proposed method can accelerate stochastic computing with small hardware cost. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Error tolerant application / Stochastic number / Transformation error / Correlation-induced error / Bit sharing / Area efficiency |
| Paper # | DC2015-89 |
| Date of Issue | 2016-02-10 (DC) |
| Conference Information | |
| Committee | DC |
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| Conference Date | 2016/2/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Chair | Nobuyasu Kanekawa(Hitachi) |
| Vice Chair | Michiko Inoue(NAIST) |
| Secretary | Michiko Inoue(RTRI) |
| Assistant | |
| Paper Information | |
| Registration To | Technical Committee on Dependable Computing |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences |
| Sub Title (in English) | |
| Keyword(1) | Error tolerant application |
| Keyword(2) | Stochastic number |
| Keyword(3) | Transformation error |
| Keyword(4) | Correlation-induced error |
| Keyword(5) | Bit sharing |
| Keyword(6) | Area efficiency |
| 1st Author's Name | Kensuke Takamori |
| 1st Author's Affiliation | Hiroshima City University(Hiroshima City Univ.) |
| 2nd Author's Name | Hideyuki Ichihara |
| 2nd Author's Affiliation | Hiroshima City University(Hiroshima City Univ.) |
| 3rd Author's Name | Tsuyoshi Iwagaki |
| 3rd Author's Affiliation | Hiroshima City University(Hiroshima City Univ.) |
| 4th Author's Name | Tomoo Inoue |
| 4th Author's Affiliation | Hiroshima City University(Hiroshima City Univ.) |
| Date | 2016-02-17 |
| Paper # | DC2015-89 |
| Volume (vol) | vol.115 |
| Number (no) | DC-449 |
| Page | pp.pp.19-24(DC), |
| #Pages | 6 |
| Date of Issue | 2016-02-10 (DC) |