Presentation 2016-02-17
Study on the Effect of Power Supply Noise on Flip-Flop Circuits
Takuya Yamamoto, Yukiya Miura,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) According to the scaling down, and lower power design of VLSI circuits, power supply noise such as IR-drop affects the operation of memory cells such as SRAM and FF circuits. Error occurrence on SRAM is already reported and some countermeasures are proposed. It is likely that further scaling down and lower power design will cause the error similar to that on SRAM for FF circuits and countermeasures will be needed. In this paper, we analyzed the effect of power supply noise on FF circuits and considered the cause of error occurrence.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Power Supply Noise / Flip-Flop / Latch / Bit-Flip / Malfunction
Paper # DC2015-96
Date of Issue 2016-02-10 (DC)

Conference Information
Committee DC
Conference Date 2016/2/17(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kikai-Shinko-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) VLSI Design and Test, etc.
Chair Nobuyasu Kanekawa(Hitachi)
Vice Chair Michiko Inoue(NAIST)
Secretary Michiko Inoue(RTRI)
Assistant

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Study on the Effect of Power Supply Noise on Flip-Flop Circuits
Sub Title (in English)
Keyword(1) Power Supply Noise
Keyword(2) Flip-Flop
Keyword(3) Latch
Keyword(4) Bit-Flip
Keyword(5) Malfunction
1st Author's Name Takuya Yamamoto
1st Author's Affiliation Tokyo Metropolitan University(Tokyo Metropolitan Univ.)
2nd Author's Name Yukiya Miura
2nd Author's Affiliation Tokyo Metropolitan University(Tokyo Metropolitan Univ.)
Date 2016-02-17
Paper # DC2015-96
Volume (vol) vol.115
Number (no) DC-449
Page pp.pp.61-66(DC),
#Pages 6
Date of Issue 2016-02-10 (DC)