Presentation 2016-02-17
A Ranking Method of Suspicious Candidate Faults Using Fault Excitation Condition Analysis for Universal Logical Fault Diagnosis
Hideyuki Takano, Toshinori Hosokawa, Hiroshi Yamazaki, Koji Yamazaki,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English)
Keyword(in Japanese) (See Japanese page)
Keyword(in English)
Paper # DC2015-91
Date of Issue 2016-02-10 (DC)

Conference Information
Committee DC
Conference Date 2016/2/17(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kikai-Shinko-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) VLSI Design and Test, etc.
Chair Nobuyasu Kanekawa(Hitachi)
Vice Chair Michiko Inoue(NAIST)
Secretary Michiko Inoue(RTRI)
Assistant

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Ranking Method of Suspicious Candidate Faults Using Fault Excitation Condition Analysis for Universal Logical Fault Diagnosis
Sub Title (in English)
Keyword(1)
1st Author's Name Hideyuki Takano
1st Author's Affiliation Nihon University(Nihon Univ.)
2nd Author's Name Toshinori Hosokawa
2nd Author's Affiliation Nihon University(Nihon Univ.)
3rd Author's Name Hiroshi Yamazaki
3rd Author's Affiliation Nihon University(Nihon Univ.)
4th Author's Name Koji Yamazaki
4th Author's Affiliation Meiji University(Meiji Univ.)
Date 2016-02-17
Paper # DC2015-91
Volume (vol) vol.115
Number (no) DC-449
Page pp.pp.31-36(DC),
#Pages 6
Date of Issue 2016-02-10 (DC)