Presentation 2016-02-17
An RTL Test Point Insertion Method to Reduce the Number of Test Patterns
Naoya Ohsaki, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Test point insertion methods to reduce the number of test patterns have been proposed for test cost reduction of VLSIs. Test point insertion methods at gate level requires an enormous amount of time to identify signal lines to insert test points for large circuits. Additional multiplexors make them damage timing optimality by logic synthesis. Thus, test point insertion methods at RTL is required. In this paper, we propose a test register allocation method for concurrent testing of functional units in scan testing using RTL test point insertion. Furthermore, we propose a controller augmentation method for guaranteeing the behavior. Experimental results show that our proposed method which is the combination of the test register allocation method and the controller augmentation method reduced the number of test patterns by 17 % on the average for benchmark circuits of high-level synthesis.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) test registers / parallel testing / conrtoller augmentation / register transfer level / test point insertion
Paper # DC2015-93
Date of Issue 2016-02-10 (DC)

Conference Information
Committee DC
Conference Date 2016/2/17(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kikai-Shinko-Kaikan Bldg.
Topics (in Japanese) (See Japanese page)
Topics (in English) VLSI Design and Test, etc.
Chair Nobuyasu Kanekawa(Hitachi)
Vice Chair Michiko Inoue(NAIST)
Secretary Michiko Inoue(RTRI)

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An RTL Test Point Insertion Method to Reduce the Number of Test Patterns
Sub Title (in English)
Keyword(1) test registers
Keyword(2) parallel testing
Keyword(3) conrtoller augmentation
Keyword(4) register transfer level
Keyword(5) test point insertion
1st Author's Name Naoya Ohsaki
1st Author's Affiliation Nihon University(NU)
2nd Author's Name Toshinori Hosokawa
2nd Author's Affiliation Nihon University(NU)
3rd Author's Name Hiroshi Yamazaki
3rd Author's Affiliation Nihon University(NU)
4th Author's Name Masayoshi Yoshimura
4th Author's Affiliation Kyoto Sangyo University(KSU)
Date 2016-02-17
Paper # DC2015-93
Volume (vol) vol.115
Number (no) DC-449
Page pp.pp.43-48(DC),
#Pages 6
Date of Issue 2016-02-10 (DC)