| Presentation | 2016-01-28 [Invited Talk] MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for high speed operation and considered not suited for higher level cache memory. In this work, we have developed L2 and L3 cache memory based on thermal stability factor engineered pMTJ with 2T-2MTJ and 1T-1MTJ memory cell and novel error handling scheme. These techniques reduce 75% energy with 2% performance overhead compared to SRAM based L2 and L3 cache memory. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | |
| Paper # | SDM2015-126 |
| Date of Issue | 2016-01-21 (SDM) |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2016/1/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Yuzou Oono(Univ. of Tsukuba) |
| Vice Chair | Tatsuya Kunikiyo(Renesas) |
| Secretary | Tatsuya Kunikiyo(Tohoku Univ.) |
| Assistant | Tadashi Yamaguchi(Renesas) |
| Paper Information | |
| Registration To | Technical Committee on Silicon Device and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited Talk] MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme |
| Sub Title (in English) | |
| Keyword(1) | |
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| 1st Author's Name | Kazutaka Ikegami |
| 1st Author's Affiliation | Toshiba Corporate(Toshiba) |
| 2nd Author's Name | Hiroki Noguchi |
| 2nd Author's Affiliation | Toshiba Corporate(Toshiba) |
| 3rd Author's Name | Satoshi Takaya |
| 3rd Author's Affiliation | Toshiba Corporate(Toshiba) |
| 4th Author's Name | Chikayoshi Kamata |
| 4th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 5th Author's Name | Minoru Amano |
| 5th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 6th Author's Name | Keiko Abe |
| 6th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 7th Author's Name | Keiichi Kushida |
| 7th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 8th Author's Name | Eiji Kitagawa |
| 8th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 9th Author's Name | Takao Ochiai |
| 9th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 10th Author's Name | Naoharu Shimomura |
| 10th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 11th Author's Name | Daisuke Saida |
| 11th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 12th Author's Name | Atsushi Kawasumi |
| 12th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 13th Author's Name | Hiroyuki Hara |
| 13th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 14th Author's Name | Junichi Ito |
| 14th Author's Affiliation | Toshiba Corporate(Toshiba) |
| 15th Author's Name | Shinobu Fujita |
| 15th Author's Affiliation | Toshiba Corporate(Toshiba) |
| Date | 2016-01-28 |
| Paper # | SDM2015-126 |
| Volume (vol) | vol.115 |
| Number (no) | SDM-440 |
| Page | pp.pp.27-30(SDM), |
| #Pages | 4 |
| Date of Issue | 2016-01-21 (SDM) |