| Presentation | 2016-01-21 Improvement of operational stability of SFQ logic gate with optimized Josephson comparator Kenta Asakura, Yuki Yamanashi, Nobuyuki Yoshikawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A single-flux-quantum (SFQ) circuits has been studied because of its low power and high-speed operation. Because the bit energy of the SFQ circuit is extremely low, careful design is required to build reliable large-scale SFQ circuit that has the ultra-low error rate. In this study, we investigated improvement of a bit-error rate of the SFQ logic gate by optimizing Josephson comparators, which is a pair of serially connected Josephson junctions and make decisions of the signal outputs, in the logic gate. We have investigated the bit error rate of SFQ logic gates that have various circuit parameters and structures. Measurements result show that the bit-error rate can be improved by optimizing SFQ OR gate. The difference is 3% at the bit-error rate of 10-4. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ / comparator / logic gate / gray zone width / bit-error rate |
| Paper # | SCE2015-37 |
| Date of Issue | 2016-01-14 (SCE) |
| Conference Information | |
| Committee | SCE |
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| Conference Date | 2016/1/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Nobuyuki Yoshikawa(Yokohama National Univ.) |
| Vice Chair | |
| Secretary | (Yokohama National Univ.) |
| Assistant | Hiroyuki Akaike(Nagoya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Superconductive Electronics |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Improvement of operational stability of SFQ logic gate with optimized Josephson comparator |
| Sub Title (in English) | |
| Keyword(1) | SFQ |
| Keyword(2) | comparator |
| Keyword(3) | logic gate |
| Keyword(4) | gray zone width |
| Keyword(5) | bit-error rate |
| 1st Author's Name | Kenta Asakura |
| 1st Author's Affiliation | Yokohama National University(Yokohama Nat Univ.) |
| 2nd Author's Name | Yuki Yamanashi |
| 2nd Author's Affiliation | Yokohama National University(Yokohama Nat Univ.) |
| 3rd Author's Name | Nobuyuki Yoshikawa |
| 3rd Author's Affiliation | Yokohama National University(Yokohama Nat Univ.) |
| Date | 2016-01-21 |
| Paper # | SCE2015-37 |
| Volume (vol) | vol.115 |
| Number (no) | SCE-412 |
| Page | pp.pp.7-10(SCE), |
| #Pages | 4 |
| Date of Issue | 2016-01-14 (SCE) |