| Presentation | 2016-01-19 A Low-Latency Batch Processing for Stream Data Using FPGA NIC Kohei Nakamura, Ami Hayashi, Hiroki Matsutani, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGAs / Accelerator design / Cache / Stream processing / Streaming data |
| Paper # | VLD2015-80,CPSY2015-112,RECONF2015-62 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | VLD / CPSY / RECONF / IPSJ-SLDM / IPSJ-ARC |
|---|---|
| Conference Date | 2016/1/19(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Masahiro Fukui(Ritsumeikan Univ.) / Masahiro Goshima(国情研) |
| Vice Chair | Takashi Takenana(NEC) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(Fujitsu Labs.) / Masato Motomura(NII) / Yuichiro Shibata(Toshiba) / (Univ. of Tsukuba) / (Sharp) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Special Interest Group on System and LSI Design Methodology / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low-Latency Batch Processing for Stream Data Using FPGA NIC |
| Sub Title (in English) | |
| Keyword(1) | FPGAs |
| Keyword(2) | Accelerator design |
| Keyword(3) | Cache |
| Keyword(4) | Stream processing |
| Keyword(5) | Streaming data |
| 1st Author's Name | Kohei Nakamura |
| 1st Author's Affiliation | Keio University(Keio Univ.) |
| 2nd Author's Name | Ami Hayashi |
| 2nd Author's Affiliation | Keio University(Keio Univ.) |
| 3rd Author's Name | Hiroki Matsutani |
| 3rd Author's Affiliation | Keio University(Keio Univ.) |
| Date | 2016-01-19 |
| Paper # | VLD2015-80,CPSY2015-112,RECONF2015-62 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-398,CPSY-399,RECONF-400 |
| Page | pp.pp.19-24(VLD), pp.19-24(CPSY), pp.19-24(RECONF), |
| #Pages | 6 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |