| Presentation | 2016-01-20 FPGA-based Tsunami Simulator developed by using stream-computing hardware compiler Kohei Nagasu, Kentaro Sano, Fumiya Kono, Naohito Nakasato, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Method of Splitting Tsunami (MOST) is a numerical solver of Shallow Water Equations (SWEs), which is used for forecasting tsunami. Tsunami Simulation using MOST is usually run with a supercomputer, however it is difficult to take a rapid responce to disaster with such a large-scale computing system. One of the solutions to this problem is development of a compact system with custom computing machines. In this paper, we use Field-Programmable Gate Arrays (FPGAs) as a platform to build a custom computing machine of Tsunami simulation based on MOST. We design Stream Processing Element (SPE) as a hardware SWEs solver by using our stream-computation hardware compiler, called SPGen. We implement hardware with a single SPE or two cascaded SPEs on 28nm ALTERA Stratix V FPGA, which achieves 51.8GFlop/s or 103.7GFlop/s, bringing the performance per power of 1.71GFlop/sW or 2.91GFlop/sW, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGAs / stream-computation / shallow water equations / method of splitting tsunami / tsunami simulator |
| Paper # | VLD2015-92,CPSY2015-124,RECONF2015-74 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | VLD / CPSY / RECONF / IPSJ-SLDM / IPSJ-ARC |
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| Conference Date | 2016/1/19(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Masahiro Fukui(Ritsumeikan Univ.) / Masahiro Goshima(国情研) |
| Vice Chair | Takashi Takenana(NEC) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(Fujitsu Labs.) / Masato Motomura(NII) / Yuichiro Shibata(Toshiba) / (Univ. of Tsukuba) / (Sharp) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Special Interest Group on System and LSI Design Methodology / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA-based Tsunami Simulator developed by using stream-computing hardware compiler |
| Sub Title (in English) | |
| Keyword(1) | FPGAs |
| Keyword(2) | stream-computation |
| Keyword(3) | shallow water equations |
| Keyword(4) | method of splitting tsunami |
| Keyword(5) | tsunami simulator |
| 1st Author's Name | Kohei Nagasu |
| 1st Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 2nd Author's Name | Kentaro Sano |
| 2nd Author's Affiliation | Tohoku University(Tohoku Univ.) |
| 3rd Author's Name | Fumiya Kono |
| 3rd Author's Affiliation | The University of Aizu(The Univ. of Aizu) |
| 4th Author's Name | Naohito Nakasato |
| 4th Author's Affiliation | The University of Aizu(The Univ. of Aizu) |
| Date | 2016-01-20 |
| Paper # | VLD2015-92,CPSY2015-124,RECONF2015-74 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-398,CPSY-399,RECONF-400 |
| Page | pp.pp.131-136(VLD), pp.131-136(CPSY), pp.131-136(RECONF), |
| #Pages | 6 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |