| Presentation | 2016-01-19 FPGA routing structure based on H-Tree topology Yuki ishii, Masato Ikebe, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | FPGA(Fiele Programmable Gate Array) has many routing resources in order to provide the flexibility. These routing resources have large impact to the peformance of FPGA. The routing congestion causes competitive of signals and routing detours which degrade the peformance of FPGA. We have been found that the effect is small portion of the high fanout nets as the cause of wiring congestion, delay in the removal of them, it has also been reported that the area can be reduced. This is a study focusing on the high fanouts net is the cause of the wiring congestion, consider the FPGA routing structure of the high fanouts net based on H-Tree topology. As a result, if it is possible to reduce the number of tracks of the homogeneous structure by the H-Tree, homogeneous structure with a H-Tree wiring was found to be very effective. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / routing structure / routing congestion / H-Tree topology |
| Paper # | VLD2015-78,CPSY2015-110,RECONF2015-60 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | VLD / CPSY / RECONF / IPSJ-SLDM / IPSJ-ARC |
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| Conference Date | 2016/1/19(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Masahiro Fukui(Ritsumeikan Univ.) / Masahiro Goshima(国情研) |
| Vice Chair | Takashi Takenana(NEC) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(Fujitsu Labs.) / Masato Motomura(NII) / Yuichiro Shibata(Toshiba) / (Univ. of Tsukuba) / (Sharp) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Special Interest Group on System and LSI Design Methodology / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA routing structure based on H-Tree topology |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | routing structure |
| Keyword(3) | routing congestion |
| Keyword(4) | H-Tree topology |
| 1st Author's Name | Yuki ishii |
| 1st Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 2nd Author's Name | Masato Ikebe |
| 2nd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 3rd Author's Name | Qian Zhao |
| 3rd Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 4th Author's Name | Motoki Amagasaki |
| 4th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 5th Author's Name | Masahiro Iida |
| 5th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 6th Author's Name | Morihiro Kuga |
| 6th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| 7th Author's Name | Toshinori Sueyoshi |
| 7th Author's Affiliation | Kumamoto University(Kumamoto Univ.) |
| Date | 2016-01-19 |
| Paper # | VLD2015-78,CPSY2015-110,RECONF2015-60 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-398,CPSY-399,RECONF-400 |
| Page | pp.pp.7-12(VLD), pp.7-12(CPSY), pp.7-12(RECONF), |
| #Pages | 6 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |