| Presentation | 2016-01-20 Design of Stencil Computation based on Building-Cube Method on an FPGA Accelerator with High Level Synthesis Rie Soejima, Koji Okina, Yuichiro Shibata, Kiyoshi Oguri, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In building-cube method (BCM), which is one of the adaptive mesh refinement, the computational region is divided into a number of sub-domains with various sizes. One of advantages of the BCM that it suits parallel processing, due to each sub-domain has a similar data size and a similar computing flow in spite of the difference in size. This paper presents implementation of a class library framework on a high-level synthesis system, which aims at enabling easy FPGA implementation of BCM-based stencil computation. The proposed framework is evaluated with a heat conduction simulation as a benchmark application in terms of computing performance, memory performance and hardware amount, so that overheads of a mechanism of data exchange between sub-domains with different size are revealed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Stencil computation / Building-cube method / High level synthesis tool / MaxCompiler / Heat conduction simulation |
| Paper # | VLD2015-91,CPSY2015-123,RECONF2015-73 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |
| Conference Information | |
| Committee | VLD / CPSY / RECONF / IPSJ-SLDM / IPSJ-ARC |
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| Conference Date | 2016/1/19(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Masahiro Fukui(Ritsumeikan Univ.) / Masahiro Goshima(国情研) |
| Vice Chair | Takashi Takenana(NEC) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(Fujitsu Labs.) / Masato Motomura(NII) / Yuichiro Shibata(Toshiba) / (Univ. of Tsukuba) / (Sharp) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Special Interest Group on System and LSI Design Methodology / Special Interest Group on System Architecture |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Stencil Computation based on Building-Cube Method on an FPGA Accelerator with High Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Stencil computation |
| Keyword(3) | Building-cube method |
| Keyword(4) | High level synthesis tool |
| Keyword(5) | MaxCompiler |
| Keyword(6) | Heat conduction simulation |
| 1st Author's Name | Rie Soejima |
| 1st Author's Affiliation | Nagasaki University(Nagasaki Univ.) |
| 2nd Author's Name | Koji Okina |
| 2nd Author's Affiliation | Nagasaki University(Nagasaki Univ.) |
| 3rd Author's Name | Yuichiro Shibata |
| 3rd Author's Affiliation | Nagasaki University(Nagasaki Univ.) |
| 4th Author's Name | Kiyoshi Oguri |
| 4th Author's Affiliation | Nagasaki University(Nagasaki Univ.) |
| Date | 2016-01-20 |
| Paper # | VLD2015-91,CPSY2015-123,RECONF2015-73 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-398,CPSY-399,RECONF-400 |
| Page | pp.pp.125-130(VLD), pp.125-130(CPSY), pp.125-130(RECONF), |
| #Pages | 6 |
| Date of Issue | 2016-01-12 (VLD, CPSY, RECONF) |