| Presentation | 2015-12-17 Improvement of TLB performance of MIPS-based processor Gun Muto, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | TLB is onw of the important modules to enhance memory access performance. Generally, increasing the number of TLB entries contributes TLB hit rate and performance improvement. However, MIPS32 ISA limits the number of TLB entries to 64. This paper proposes mechanism to increase TLB entries without breaking binary compatibility. Our approach analyzes executing code related to TLB access dynamically, and behaves like 64-entry TLB. According to our simulation results, our approach can improve TLB hit rate without breaking binary compatibility. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | TLB / MIPS / high performance / embedded processor |
| Paper # | ICD2015-65,CPSY2015-78 |
| Date of Issue | 2015-12-10 (ICD, CPSY) |
| Conference Information | |
| Committee | ICD / CPSY |
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| Conference Date | 2015/12/17(2days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyoto Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | Minoru Fujishima(Hiroshima Univ.) / Yasuhiko Nakashima(NAIST) |
| Vice Chair | Hideto Hidaka(Renesas) / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) |
| Secretary | Hideto Hidaka(Hiroshima Univ.) / Koji Nakano(Fujitsu Labs.) / Hidetsugu Irie(NII) |
| Assistant | Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) |
| Paper Information | |
| Registration To | Technical Committee on Integrated Circuits and Devices / Technical Committee on Computer Systems |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Improvement of TLB performance of MIPS-based processor |
| Sub Title (in English) | |
| Keyword(1) | TLB |
| Keyword(2) | MIPS |
| Keyword(3) | high performance |
| Keyword(4) | embedded processor |
| 1st Author's Name | Gun Muto |
| 1st Author's Affiliation | Mie University(Mie Univ.) |
| 2nd Author's Name | Takahiro Sasaki |
| 2nd Author's Affiliation | Mie University(Mie Univ.) |
| 3rd Author's Name | Yuki Fukazawa |
| 3rd Author's Affiliation | Mie University(Mie Univ.) |
| 4th Author's Name | Toshio Kondo |
| 4th Author's Affiliation | Mie University(Mie Univ.) |
| Date | 2015-12-17 |
| Paper # | ICD2015-65,CPSY2015-78 |
| Volume (vol) | vol.115 |
| Number (no) | ICD-373,CPSY-374 |
| Page | pp.pp.13-18(ICD), pp.13-18(CPSY), |
| #Pages | 6 |
| Date of Issue | 2015-12-10 (ICD, CPSY) |