Presentation 2015-12-14
Memory Application of Ultrafine FET utilizing Supramolecular Protein
Takahiko Ban, Mutsunori Uenuma, Shinji Migita, Yasuaki Ishikawa, Ichiro Yamashita, Yukiharu Uraoka,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Metal nanoparticles (NPs) embedded in junctionless field-effect transistors (JL-FETs) with a length of 3.6 nm is fabricated and demonstrated. The anisotropic wet etching of a silicon-on-insulator (SOI) substrate was utilized to form V-grooves and to define nanometer-scale channel. Metal NPs are selectively placed onto bottom of V-groove using the Baio nano process (BNP). The JL-FET is applied to floating gate memory and used to investigate an impact on the short channel by charge trap of NPs. Low-voltage operation and broad threshold voltage shift as memory behavior are appeared in 3.6 nm channel length. It is expected that the JL-FETs can overcome the scaling limitations in floating gate memory, while the charge trap cause major problems in the sub 10 nm region.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Bio Nano Process / Junctionless-FET / Nano-particle / Memory
Paper # EID2015-11,SDM2015-94
Date of Issue 2015-12-07 (EID, SDM)

Conference Information
Committee EID / SDM
Conference Date 2015/12/14(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Ryukoku University, Avanti Kyoto Hall
Topics (in Japanese) (See Japanese page)
Topics (in English) Si and Si-related Materials and Devices, and Display Technology
Chair Tomokazu Shiga(Univ. of Electro-Comm.) / Yuzou Oono(Univ. of Tsukuba)
Vice Chair Mutsumi Kimura(Ryukoku Univ.) / Yuko Kominami(Shizuoka Univ.) / Tatsuya Kunikiyo(Renesas)
Secretary Mutsumi Kimura(NTT) / Yuko Kominami(Tokyo Inst. of Tech.) / Tatsuya Kunikiyo(Tohoku Univ.)
Assistant Rumiko Yamaguchi(Akita Univ.) / Hiroyuki Nitta(Japan Display) / Mitsuru Nakata(NHK) / Takashi Kojiri(ZEON) / Ryosuke Nonaka(Toshiba) / Takeshi Okuno(Samsung) / Tadashi Yamaguchi(Renesas)

Paper Information
Registration To Technical Committee on Electronic Information Displays / Technical Committee on Silicon Device and Materials
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Memory Application of Ultrafine FET utilizing Supramolecular Protein
Sub Title (in English)
Keyword(1) Bio Nano Process
Keyword(2) Junctionless-FET
Keyword(3) Nano-particle
Keyword(4) Memory
1st Author's Name Takahiko Ban
1st Author's Affiliation Nara Insutitute of Science and Technology(NAIST)
2nd Author's Name Mutsunori Uenuma
2nd Author's Affiliation Nara Insutitute of Science and Technology(NAIST)
3rd Author's Name Shinji Migita
3rd Author's Affiliation National Institute of Advanced Industrial Science and Technology(AIST)
4th Author's Name Yasuaki Ishikawa
4th Author's Affiliation Nara Insutitute of Science and Technology(NAIST)
5th Author's Name Ichiro Yamashita
5th Author's Affiliation Nara Insutitute of Science and Technology(NAIST)
6th Author's Name Yukiharu Uraoka
6th Author's Affiliation Nara Insutitute of Science and Technology(NAIST)
Date 2015-12-14
Paper # EID2015-11,SDM2015-94
Volume (vol) vol.115
Number (no) EID-362,SDM-363
Page pp.pp.9-12(EID), pp.9-12(SDM),
#Pages 4
Date of Issue 2015-12-07 (EID, SDM)