Presentation 2015-12-18
Error Correcting Codes Considering P/E Cycles for NAND Flash Memories
Mampei Asai, Masato Kitakami,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) I Recently, multi-level cell (MLC) NAND flash memory, which has memory cells capable to store 2 or more bits of information, is widely used in order to achieve high memory density. Since the dominant error in the MLC NAND flash memory is unidirectional 1-level error, a code which can correct such errors has been proposed. In NAND flash memory, erase operation is necessary before program (writing) operation. This continuous erase - program operation is called P/E cycle. As the number of P/E operations increases, the probability of multiple symbol error cannot be neglectable. The unidirectional 1-level error correcting code cannot correct these errors. This paper proposes an error correcting method which counts the number of P/E cycles of each memory cell. The proposed method applies unidirectional 1-level error correcting code at first; and applies multi symbol error correcting code if the number of P/E cycles exceeds the predetermined value. Evaluation shows that the proposed method can switch error correcting code maintaining low error rate of the decoded data.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) NAND Flash Memory / Error Correcting Code / P/E Cycle
Paper # DC2015-76
Date of Issue 2015-12-11 (DC)

Conference Information
Committee DC
Conference Date 2015/12/18(1days)
Place (in Japanese) (See Japanese page)
Place (in English) Kurieito Mulakami (Murakami City)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair Nobuyasu Kanekawa(Hitachi)
Vice Chair Michiko Inoue(NAIST)
Secretary Michiko Inoue(RTRI)
Assistant

Paper Information
Registration To Technical Committee on Dependable Computing
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Error Correcting Codes Considering P/E Cycles for NAND Flash Memories
Sub Title (in English)
Keyword(1) NAND Flash Memory
Keyword(2) Error Correcting Code
Keyword(3) P/E Cycle
1st Author's Name Mampei Asai
1st Author's Affiliation Chiba University(Chiba Univ.)
2nd Author's Name Masato Kitakami
2nd Author's Affiliation Chiba University(Chiba Univ.)
Date 2015-12-18
Paper # DC2015-76
Volume (vol) vol.115
Number (no) DC-382
Page pp.pp.17-22(DC),
#Pages 6
Date of Issue 2015-12-11 (DC)