| Presentation | 2015-12-14 Operation verification of neural network using a simplified element by FPGA Nao Nakamura, Ryuhei Morita, Yuki Koga, Hiroki Nakanishi, Sumio Sugisaki, Tomoharu Yokoyama, Koki Watada, Tokiyoshi Matsuda, Mutsumi Kimura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Neural networks are those that aim to realize advanced information processing functions of the brain and nervous system of a living body. We are developing neural networks using thin-film transistors. To ensure the large number of neurons, it is essential to develop a simplified neurons. Therefore, we prepared three types of neuron circuits and verified the operation by FPGA. As a result, we succeeded in operating all circuits properly. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Neural Network / Simplified Element / FPGA |
| Paper # | EID2015-23,SDM2015-106 |
| Date of Issue | 2015-12-07 (EID, SDM) |
| Conference Information | |
| Committee | EID / SDM |
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| Conference Date | 2015/12/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ryukoku University, Avanti Kyoto Hall |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Si and Si-related Materials and Devices, and Display Technology |
| Chair | Tomokazu Shiga(Univ. of Electro-Comm.) / Yuzou Oono(Univ. of Tsukuba) |
| Vice Chair | Mutsumi Kimura(Ryukoku Univ.) / Yuko Kominami(Shizuoka Univ.) / Tatsuya Kunikiyo(Renesas) |
| Secretary | Mutsumi Kimura(NTT) / Yuko Kominami(Tokyo Inst. of Tech.) / Tatsuya Kunikiyo(Tohoku Univ.) |
| Assistant | Rumiko Yamaguchi(Akita Univ.) / Hiroyuki Nitta(Japan Display) / Mitsuru Nakata(NHK) / Takashi Kojiri(ZEON) / Ryosuke Nonaka(Toshiba) / Takeshi Okuno(Samsung) / Tadashi Yamaguchi(Renesas) |
| Paper Information | |
| Registration To | Technical Committee on Electronic Information Displays / Technical Committee on Silicon Device and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Operation verification of neural network using a simplified element by FPGA |
| Sub Title (in English) | |
| Keyword(1) | Neural Network |
| Keyword(2) | Simplified Element |
| Keyword(3) | FPGA |
| 1st Author's Name | Nao Nakamura |
| 1st Author's Affiliation | Ryukoku University(Ryukoku Univ.) |
| 2nd Author's Name | Ryuhei Morita |
| 2nd Author's Affiliation | Ryukoku University(Ryukoku Univ.) |
| 3rd Author's Name | Yuki Koga |
| 3rd Author's Affiliation | Ryukoku University(Ryukoku Univ.) |
| 4th Author's Name | Hiroki Nakanishi |
| 4th Author's Affiliation | Ryukoku University(Ryukoku Univ.) |
| 5th Author's Name | Sumio Sugisaki |
| 5th Author's Affiliation | Ryukoku University(Ryukoku Univ.) |
| 6th Author's Name | Tomoharu Yokoyama |
| 6th Author's Affiliation | Ryukoku University(Ryukoku Univ.) |
| 7th Author's Name | Koki Watada |
| 7th Author's Affiliation | Ryukoku University(Ryukoku Univ.) |
| 8th Author's Name | Tokiyoshi Matsuda |
| 8th Author's Affiliation | Ryukoku University(Ryukoku Univ.) |
| 9th Author's Name | Mutsumi Kimura |
| 9th Author's Affiliation | Ryukoku University(Ryukoku Univ.) |
| Date | 2015-12-14 |
| Paper # | EID2015-23,SDM2015-106 |
| Volume (vol) | vol.115 |
| Number (no) | EID-362,SDM-363 |
| Page | pp.pp.61-64(EID), pp.61-64(SDM), |
| #Pages | 4 |
| Date of Issue | 2015-12-07 (EID, SDM) |