| Presentation | 2015-12-03 A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, due to low leakage power and non-volatility, the non-volatile memory technology has advanced remarkably. However, there are two potential problems. First, high energy is required in writing data to a non-volatile memory. Secondly, write-endurance of non-volatile memories is low. Bit-level write-reduction methods solve the above problems but their encoders/decoders' area are too much large. In this paper, we propose an area-aware bit-level write-reduction code generation algorithm to solve the above problems. We also propose an evaluation system to generate small-sized encoders. Experimental results confirm the efficiency of our encoder design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Non-volatile memory / Writing-reduction code / Encoding/decoding |
| Paper # | VLD2015-76,DC2015-72 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories |
| Sub Title (in English) | |
| Keyword(1) | Non-volatile memory |
| Keyword(2) | Writing-reduction code |
| Keyword(3) | Encoding/decoding |
| 1st Author's Name | Masashi Tawada |
| 1st Author's Affiliation | Waseda University(Waseda Univ.) |
| 2nd Author's Name | Shinji Kimura |
| 2nd Author's Affiliation | Waseda University(Waseda Univ.) |
| 3rd Author's Name | Masao Yanagisawa |
| 3rd Author's Affiliation | Waseda University(Waseda Univ.) |
| 4th Author's Name | Nozomu Togawa |
| 4th Author's Affiliation | Waseda University(Waseda Univ.) |
| Date | 2015-12-03 |
| Paper # | VLD2015-76,DC2015-72 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.249-253(VLD), pp.249-253(DC), |
| #Pages | 5 |
| Date of Issue | 2015-11-24 (VLD, DC) |