| Presentation | 2015-12-02 Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating Masaru Kudo, Kimiyoshi Usami, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a sleep control technique using leakage monitor circuit to implement Fine-Grain Power Gating (FGPG). This technique controls Power Switch (PS) by leakage monitor circuit. This technique enables us to reduce energy overhead due to sleep control circuit and realize efficient power gating depending on temperature. We evaluated leakage energy dissipation by using simulation for microprocessor which applied FGPG. The impact of process variations is also discussed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Fine-Grain Power Gating / Leakage Monitor / Low Power |
| Paper # | VLD2015-57,DC2015-53 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating |
| Sub Title (in English) | |
| Keyword(1) | Fine-Grain Power Gating |
| Keyword(2) | Leakage Monitor |
| Keyword(3) | Low Power |
| 1st Author's Name | Masaru Kudo |
| 1st Author's Affiliation | Shibaura Institute of Technology(Shibaura Institute of Tech.) |
| 2nd Author's Name | Kimiyoshi Usami |
| 2nd Author's Affiliation | Shibaura Institute of Technology(Shibaura Institute of Tech.) |
| Date | 2015-12-02 |
| Paper # | VLD2015-57,DC2015-53 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.129-134(VLD), pp.129-134(DC), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |