Presentation | 2015-12-02 A low-power soft error tolerant latch scheme on 15nm process Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In recent technology scaling, reliability of integrated circuits due to a soft error is becoming more critical than ever before. In literature, several soft error tolerant techniques have been proposed. However due to the power constraints, new techniques for high-tolerant and low-power are needed. In this paper, we propose a New-SEH latch design, and implement it in NCSU 15nm technology. The simulation results show that the proposed latch obtains up to 84.39$%$ power reduction compared to SEH latch. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Power / Soft Error Hardened (SEH) Latch / Soft error |
Paper # | VLD2015-56,DC2015-52 |
Date of Issue | 2015-11-24 (VLD, DC) |
Conference Information | |
Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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Conference Date | 2015/12/1(3days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | Nagasaki Kinro Fukushi Kaikan |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
Paper Information | |
Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A low-power soft error tolerant latch scheme on 15nm process |
Sub Title (in English) | |
Keyword(1) | Power |
Keyword(2) | Soft Error Hardened (SEH) Latch |
Keyword(3) | Soft error |
Keyword(4) | |
1st Author's Name | Saki Tajima |
1st Author's Affiliation | Waseda University(Waseda Univ.) |
2nd Author's Name | Youhua Shi |
2nd Author's Affiliation | Waseda University(Waseda Univ.) |
3rd Author's Name | Nozomu Togawa |
3rd Author's Affiliation | Waseda University(Waseda Univ.) |
4th Author's Name | Masao Yanagisawa |
4th Author's Affiliation | Waseda University(Waseda Univ.) |
Date | 2015-12-02 |
Paper # | VLD2015-56,DC2015-52 |
Volume (vol) | vol.115 |
Number (no) | VLD-338,DC-339 |
Page | pp.pp.123-127(VLD), pp.123-127(DC), |
#Pages | 5 |
Date of Issue | 2015-11-24 (VLD, DC) |