Presentation 2015-12-02
Performance Comparison of FPGA Accelerators with Vivado HLS and PyCoRAM
Yuma Kikutani, Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) High-level synthesis (HLS) technology has been an attractive and efficient method for FPGA system development. In this paper, we developed matrix multiplication accelerators by using two different HLS tools: PyCoRAM, an open sourced HLS tool in Python, and Vivado HLS, a commercial HLS tool. Then we evaluated the performance by using an ARM-based FPGA platform. The evaluation result shows that the accelerator using PyCoRAM is faster than the one using Vivado HLS. It indicates that an explicit tuning way and the predictability of the performance are important for high performance system development with HLS tools. In addition, FPGA accelerators we developed could not overcome the CPU on the same board, due to its narrower memory bandwidth to the external DRAM than the CPU. It shows that a wider interconnection to the external memory is required to achieve higher performance than the CPU.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / High Level Synthesis / Vivado HLS / PyCoRAM
Paper # CPSY2015-66
Date of Issue 2015-11-24 (CPSY)

Conference Information
Committee VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM
Conference Date 2015/12/1(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Nagasaki Kinro Fukushi Kaikan
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2015 -New Field of VLSI Design-
Chair Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.)
Vice Chair Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.)
Secretary Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII)
Assistant Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Performance Comparison of FPGA Accelerators with Vivado HLS and PyCoRAM
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) High Level Synthesis
Keyword(3) Vivado HLS
Keyword(4) PyCoRAM
1st Author's Name Yuma Kikutani
1st Author's Affiliation Osaka Prefecture University College of Technology(OPUCT)
2nd Author's Name Thi Hong Tran
2nd Author's Affiliation Nara Institute of Science and Technology(NAIST)
3rd Author's Name Shinya Takamaeda
3rd Author's Affiliation Nara Institute of Science and Technology(NAIST)
4th Author's Name Yasuhiko Nakashima
4th Author's Affiliation Nara Institute of Science and Technology(NAIST)
Date 2015-12-02
Paper # CPSY2015-66
Volume (vol) vol.115
Number (no) CPSY-342
Page pp.pp.27-32(CPSY),
#Pages 6
Date of Issue 2015-11-24 (CPSY)