| Presentation | 2015-12-03 An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components Junghoon Oh, Mineo Kaneko, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the device size decreases, the reliability degradation due to soft-errors is becoming one of the serious issues in VLSIs. Concerning the tolerability against multiple component error caused by a single soft-error in our design, we use the combination of comparison-retry mechanism and vote mechanism to realize on-line error correction. Under the assumption that a single soft-error does not affect beyond a certain spatial range, we consider the adjacency constraint between components in datapath. By introducing the adjacency constraint, the chance of speculative resource sharing can be increased, 3 triplicated computation algorithms can be executed in parallel, and as a result, total schedule length can be improved. The experimental result revealed that our approach can reduce the latency in many applications compared with conventional methods. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Soft-Error / Fault Tolerance / Component Adjacency Constraint / High-Level Synthesis / Triple Algorithm Redundancy |
| Paper # | VLD2015-62,DC2015-58 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components |
| Sub Title (in English) | |
| Keyword(1) | Soft-Error |
| Keyword(2) | Fault Tolerance |
| Keyword(3) | Component Adjacency Constraint |
| Keyword(4) | High-Level Synthesis |
| Keyword(5) | Triple Algorithm Redundancy |
| 1st Author's Name | Junghoon Oh |
| 1st Author's Affiliation | Japan Advanced Institute Science and Technology(JAIST) |
| 2nd Author's Name | Mineo Kaneko |
| 2nd Author's Affiliation | Japan Advanced Institute Science and Technology(JAIST) |
| Date | 2015-12-03 |
| Paper # | VLD2015-62,DC2015-58 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.159-164(VLD), pp.159-164(DC), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |