| Presentation | 2015-12-03 On Correction of Temperature Influence to Delay Measurement in FPGAs Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As a means for delay testing for VLSIs in field, a measurement method of a path delay for a logic circuit using variable test timing has been proposed. However, the measured delay in the field is varied by temperature at test, because the temperature affects the circuit delay in the chip. Correction of influence by temperature variation upon the delay is required in order to compare the measured delay at different times. In this paper, the influence of the temperature during testing on the measured delay value is evaluated using a delay measurement circuit in an FPGA. Then, this paper proposes a correction technique of temperature influence on the measured delay using on-chip delay measurement, in order to realize delay measurement which does not depend on the temperature during testing in the field. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Logic BIST / Delay measurement / Variable test timing |
| Paper # | VLD2015-63,DC2015-59 |
| Date of Issue | 2015-11-24 (VLD, DC) |
| Conference Information | |
| Committee | VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM |
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| Conference Date | 2015/12/1(3days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Chair | Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.) |
| Vice Chair | Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.) |
| Secretary | Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII) |
| Assistant | Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.) |
| Paper Information | |
| Registration To | Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On Correction of Temperature Influence to Delay Measurement in FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Logic BIST |
| Keyword(3) | Delay measurement |
| Keyword(4) | Variable test timing |
| 1st Author's Name | Takeru Kina |
| 1st Author's Affiliation | Kyushu Institute of Technology(KIT) |
| 2nd Author's Name | Yousuke Miyake |
| 2nd Author's Affiliation | Kyushu Institute of Technology(KIT) |
| 3rd Author's Name | Yasuo Sato |
| 3rd Author's Affiliation | Kyushu Institute of Technology(KIT) |
| 4th Author's Name | Seiji Kajihara |
| 4th Author's Affiliation | Kyushu Institute of Technology(KIT) |
| Date | 2015-12-03 |
| Paper # | VLD2015-63,DC2015-59 |
| Volume (vol) | vol.115 |
| Number (no) | VLD-338,DC-339 |
| Page | pp.pp.165-170(VLD), pp.165-170(DC), |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |