Presentation 2015-12-01
Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit
Masato Tamura, Makoto Ikeda,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this paper, we investigated the implementation method of elliptic curve digital signature algorithm using self-synchronous circuit, which is a kind of asynchronous circuits. High speed and tamper resistance is important in the implementation of encryption circuit. With self-synchronous circuit, it is possible to achieve high throughput by taking a dual pipeline structure. It is also difficult to predict operation from the outside by eliminating the clock so it can achieve high tamper resistance. In the operation of ECDSA, it is essential to perform modular multiplication efficiently, so we use Montgomery multiplier in this research. In Montgomery multiplier, high speed and implementation area are trade-off relation, each of which varies depending on radix. So we change the radix of the Montgomery multiplier to investigate the operation speed and implementation area. As a result of a comparison of the circuit that has been generated by the logic synthesis , the efficiency of the self-synchronous circuit is best for synchronous circuit at the radix 256bit. The area of self-synchronous circuit is about 27 times that of synchronous circuit and throughput of self-synchronous circuit is about 2 times that of the synchronous circuit.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) self-synchronous circuit / elliptic curve cryptography / high-radix / montgomery multiplier
Paper # VLD2015-39,DC2015-35
Date of Issue 2015-11-24 (VLD, DC)

Conference Information
Committee VLD / DC / IPSJ-SLDM / CPSY / RECONF / ICD / CPM
Conference Date 2015/12/1(3days)
Place (in Japanese) (See Japanese page)
Place (in English) Nagasaki Kinro Fukushi Kaikan
Topics (in Japanese) (See Japanese page)
Topics (in English) Design Gaia 2015 -New Field of VLSI Design-
Chair Yusuke Matsunaga(Kyushu Univ.) / Nobuyasu Kanekawa(Hitachi) / Masahiro Fukui(Ritsumeikan Univ.) / Yasuhiko Nakashima(NAIST) / Minoru Watanabe(Shizuoka Univ.) / Minoru Fujishima(Hiroshima Univ.) / Satoru Noge(Numazu National College of Tech.)
Vice Chair Takashi Takenana(NEC) / Michiko Inoue(NAIST) / / Koji Nakano(Hiroshima Univ.) / Hidetsugu Irie(Univ. of Tokyo) / Masato Motomura(Hokkaido Univ.) / Yuichiro Shibata(Nagasaki Univ.) / Hideto Hidaka(Renesas) / Fumihiko Hirose(Yamagata Univ.)
Secretary Takashi Takenana(Ritsumeikan Univ.) / Michiko Inoue(Fujitsu Labs.) / (RTRI) / Koji Nakano(Kyoto Sangyo Univ.) / Hidetsugu Irie(Sharp) / Masato Motomura(Kitakyushu City Univ.) / Yuichiro Shibata(Toshiba) / Hideto Hidaka(Fujitsu Labs.) / Fumihiko Hirose(NII)
Assistant Ittetsu Taniguchi(Ritsumeikan Univ.) / / / Shinya Takameda(NAIST) / Takeshi Ohkawa(Utsunomiya Univ.) / Kazuya Tanikagawa(Hiroshima City Univ.) / Takefumi Miyoshi(e-trees.Japan) / Makoto Takamiya(Univ. of Tokyo) / Hiroe Iwasaki(NTT) / Takashi Hashimoto(Panasonic) / Hiroyuki Ito(Tokyo Inst. of Tech.) / Pham Konkuha(Univ. of Electro-Comm.) / Takashi Sakamoto(NTT) / Yuichi Nakamura(Toyohashi Univ. of Tech.)

Paper Information
Registration To Technical Committee on VLSI Design Technologies / Technical Committee on Dependable Computing / Special Interest Group on System and LSI Design Methodology / Technical Committee on Computer Systems / Technical Committee on Reconfigurable Systems / Technical Committee on Integrated Circuits and Devices / Technical Committee on Component Parts and Materials
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit
Sub Title (in English)
Keyword(1) self-synchronous circuit
Keyword(2) elliptic curve cryptography
Keyword(3) high-radix
Keyword(4) montgomery multiplier
1st Author's Name Masato Tamura
1st Author's Affiliation The University of Tokyo(Univ. of Tokyo)
2nd Author's Name Makoto Ikeda
2nd Author's Affiliation The University of Tokyo(Univ. of Tokyo)
Date 2015-12-01
Paper # VLD2015-39,DC2015-35
Volume (vol) vol.115
Number (no) VLD-338,DC-339
Page pp.pp.7-12(VLD), pp.7-12(DC),
#Pages 6
Date of Issue 2015-11-24 (VLD, DC)